International Journal of Information Engineering and Electronic Business(IJIEEB)
ISSN: 2074-9023 (Print), ISSN: 2074-9031 (Online)
Published By: MECS Press
IJIEEB Vol.10, No.1, Jan. 2018
Novel Design of 32-bit Asynchronous (RISC) Microprocessor & its Implementation on FPGA
Full Text (PDF, 1290KB), PP.39-47
As the efficiency and power consumption plays an important role in electronic system design, an asynchronous design is used to reduce such challenges faced in synchronous architectures. The asynchronous processors have a number of advantages, especially in SoC (System on chip) including reduced crosstalk between analog and digital circuits, ease of integrating multi-rate circuits, ease of component reuse and less power consumption as well. This paper deals with the novel design and implementation of such type of asynchronous microprocessor by using VHDL on Xilinx ISE tool wherein it has the capability of handling even I-Type, R-Type and Jump instructions with multiplier instruction packet. Moreover, it uses separate memory for instructions and data read-write that can be changed at any time.
Cite This Paper
Archana Rani, Naresh Grover," Novel Design of 32-bit Asynchronous (RISC) Microprocessor & its Implementation on FPGA", International Journal of Information Engineering and Electronic Business(IJIEEB), Vol.10, No.1, pp. 39-47, 2018. DOI: 10.5815/ijieeb.2018.01.06
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Wikipedia https://en.wikipedia.org/wiki/Asynchronous_circuit http://www.alteraforum.com/forum/forum.php
MIPS Instruction set architecture https://classes.soe.ucsc.edu/cmpe110/Spring11/lectures/04_MIPS_ISA%20.pdf
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