INFORMATION CHANGE THE WORLD

International Journal of Information Engineering and Electronic Business(IJIEEB)

ISSN: 2074-9023 (Print), ISSN: 2074-9031 (Online)

Published By: MECS Press

IJIEEB Vol.4, No.1, Feb. 2012

Technical Study on Low Power VLSI methods

Full Text (PDF, 214KB), PP.60-70


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Author(s)

T.Kapilachander,I.Hameem Shanavas,V.Venkataraman

Index Terms

Logic restructuring,Clock tree and clock Gating,Transistor Sizing,Pin swapping,multi-threshold voltage,Dynamic voltage scaling,DVFS,power gating,Memory splitting,Substrate biasing

Abstract

In recent days every application must need power management. In this paper we presented a various techniques to handle the power management in IC. Power dissipation in a IC is base on power used by the IC and also by heat dissipation. To reduce energy use or to minimize heat dissipation some of the techniques are briefly discussed in this paper. Power management is becoming an increasingly urgent problem for almost every category of design and application, as power density, measured in watts per square millimeter, rises at an alarming rate. Power needs to be considered at the very early stages of a design, when the opportunity to save power is at a maximum. At the same time, making a design extremely power efficient results in trading off area and/or timing. For a Integrated Circuit (IC) perspective, effective energy management for a SoC (System-on-a-chip) must be built into the design starting at the architecture stage; and low-power techniques need to be employed at every stage of the design, from RTL (Register Transfer Level) to GDSII. This paper explains about the combination of techniques used for low power approach in integrated circuits (IC) or Chip

Cite This Paper

T.Kapilachander,I.Hameem Shanavas,V.Venkataraman,"Technical Study on Low Power VLSI methods", IJIEEB, vol.4, no.1, pp.60-70, 2012.

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