International Journal of Information Engineering and Electronic Business(IJIEEB)
ISSN: 2074-9023 (Print), ISSN: 2074-9031 (Online)
Published By: MECS Press
IJIEEB Vol.4, No.4, Aug. 2012
Design Of High Performance Reconfigurable Routers Using Fpga
Full Text (PDF, 666KB), PP.46-52
Network-on-chip(NoC) architectures are emerging for the highly scalable, reliable, and modular on-chip communication infrastructure platform. The NoC architecture uses layered protocols and packet-switched networks which consist of on-chip routers, links, and network interfaces on a predefined topology. In this Project, we design network-on-chip which is based on the Cartesian network environment. This project proposes the new Cartesian topology which is used to reduce network routing time, and it is a suitable alternate to network design and implementation. The Cartesian Network-On-Chip can be modeled using Verilog HDL and simulated using Modelsim software.
Cite This Paper
R.Parthasarathi,P.Karunakaran,S.Venkatraman,T.R.DineshKumar,I.Hameem Shanavas,"Design Of High Performance Reconfigurable Routers Using Fpga", IJIEEB, vol.4, no.4, pp.46-52, 2012.
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