International Journal of Information Engineering and Electronic Business(IJIEEB)

ISSN: 2074-9023 (Print), ISSN: 2074-9031 (Online)

Published By: MECS Press

IJIEEB Vol.4, No.4, Aug. 2012

Design Of High Performance Reconfigurable Routers Using Fpga

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R.Parthasarathi,P.Karunakaran,S.Venkatraman,T.R.DineshKumar,I.Hameem Shanavas

Index Terms

Network-on-chip, Cartesian Network, Router, Verilog HDL, Architecture


Network-on-chip(NoC) architectures are emerging for the highly scalable, reliable, and modular on-chip communication infrastructure platform. The NoC architecture uses layered protocols and packet-switched networks which consist of on-chip routers, links, and network interfaces on a predefined topology. In this Project, we design network-on-chip which is based on the Cartesian network environment. This project proposes the new Cartesian topology which is used to reduce network routing time, and it is a suitable alternate to network design and implementation. The Cartesian Network-On-Chip can be modeled using Verilog HDL and simulated using Modelsim software.

Cite This Paper

R.Parthasarathi,P.Karunakaran,S.Venkatraman,T.R.DineshKumar,I.Hameem Shanavas,"Design Of High Performance Reconfigurable Routers Using Fpga", IJIEEB, vol.4, no.4, pp.46-52, 2012.


[1]Lee, Se-Joong Lee, and Hoi-Jun Yoo, "Low-Power Network-on-Chip for High-Performance SoC Design Kangmin" "IEEE transactions on very large scale integration (vlsi) systems," vol. 14, no. 2, february 2006.

[2]W. Dally et al., "Route packets, not wires: On-chip interconnection networks,"in Proc. Des. Autom. Conf., Jun. 2001, pp. 684–689.

[3]L. Benini et al., "Networks on chips: A new SoC paradigm," IEEE Computer,vol. 36, no. 1, pp. 70–78, Jan. 2002.

[4]D. Bertozzi et al., "Xpipes: A network-on-chip architecture for gigascale system-on-chip," IEEE Circuits Syst. Mag., vol. 4, no. 2, pp. 18–31,2004.

[5]E. Rijpkema et al., "Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip," in Proc. Des., Autom. Test Europe Conf., Mar. 2003, pp. 350–355.

[6]V. Nollet et al., "Operating-system controlled network on chip," in Proc. Des. Autom. Conf., Jun. 2004, pp. 256–259.

[7]C. Wu and H. Chi, "Design of a high-performance switch for circuit-switched on-chip networks," in Proc. Asian Solid-State Circuits Conf. , 2005, pp. 481–484.

[8]M. A. Al Faruque, T. Ebi, and J. Henkel, "ROAdNoC: Runtime observability for an adaptive network on chip architecture," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des. (ICCAD) , 2008, pp. 543–548.

[9]H. Jingcao, U. Y. Ogras, and R. Marculescu, "System-level buffer allo-cation for application-specific networks-on-chip router design," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. , vol. 25, no. 12, pp. 2919–2933, Dec. 2006.

[10]Y.-C. Lan, S.-H. Lo, Y.-C. Lin, Y.-H. Hu and S.-J. Chen, "BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel," in Proc. Int. Symp. Netw.-on-Chip, 2009, pp. 266–275.

[11]C. Xuning and L. Peh, "Leakage power modeling and optimization in interconnection networks," in Proc. Int. Symp. Low Power Electron.Des. (ISLPED), 2003, pp. 90–95

[12]M. Vestias and H. Neto, "Router design for application specific network-on-chip on reconfigurable systems," Field Program. Logic Appl., vol. 1, pp. 389–394, 2007