International Journal of Information Engineering and Electronic Business(IJIEEB)

ISSN: 2074-9023 (Print), ISSN: 2074-9031 (Online)

Published By: MECS Press

IJIEEB Vol.5, No.2, Aug. 2013

Cost Modeling for SOC Modules Testing

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Balwinder Singh,Arun Khosla,Sukhleen B. Narang

Index Terms

Cost modeling;System on Chip;VLSI Testing;Cost Estimation Tool


The complexity of the system design is increasing very rapidly as the number of transistors on Integrated Circuits (IC) doubles as per Moore’s law. There is big challenge of testing this complex VLSI circuit, in which whole system is integrated into a single chip called System on Chip (SOC). Cost of testing the SOC is also increasing with complexity. Cost modeling plays a vital role in reduction of test cost and time to market. This paper includes the cost modeling of the SOC Module testing which contains both analog and digital modules. The various test cost parameters and equations are considered from the previous work. The mathematical relations are developed for cost modeling to test the SOC further cost modeling equations are modeled in Graphical User Interface (GUI) in MATLAB, which can be used as a cost estimation tool. A case study is done to calculate the cost of the SOC testing due to Logic Built in Self Test (LBIST) and Memory Built in Self Test (MBIST). VLSI Test engineers can take the benefits of such cost estimation tools for test planning.

Cite This Paper

Balwinder Singh,Arun Khosla,Sukhleen B. Narang,"Cost Modeling for SOC Modules Testing", IJIEEB, vol.5, no.2, pp.1-7, 2013. DOI: 10.5815/ijieeb.2013.02.01


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