INFORMATION CHANGE THE WORLD

International Journal of Information Engineering and Electronic Business(IJIEEB)

ISSN: 2074-9023 (Print), ISSN: 2074-9031 (Online)

Published By: MECS Press

IJIEEB Vol.7, No.4, Jul. 2015

A New Partial Product Reduction Algorithm using Modified Counter and Optimized Hybrid Network

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Author(s)

Pouya Asadi

Index Terms

Adder;Booth encoder;CMOS;Multiplier;VLSI

Abstract

In this paper, a new multiplier is presented which uses modified fourteen transistor adder and optimized hybrid counter for partial product reduction step. Conventional adder is modified to improve Wallace tree functionality. Reducing critical path in counter structure can reduce VLSI area in whole multiplier structure. This paper uses a new structure in partial product reduction step to increase speed. Four to two compressors are used in modified Wallace structure to minimize the critical path. In final addition step of algorithm a new carry lookahead network is presented which adds two final operands efficiently. It uses dynamic CMOS in transistor level to reduce power consumption. Proposed multiplier reduces critical path, increases speed and decreases wiring problems in compare with previous algorithms efficiently. A new Booth encoder is presented in radix 16 circuitry. It decreases number of partial products while hardware overhead is minimized.

Cite This Paper

Pouya Asadi,"A New Partial Product Reduction Algorithm using Modified Counter and Optimized Hybrid Network", IJIEEB, vol.7, no.4, pp.1-8, 2015. DOI: 10.5815/ijieeb.2015.04.01

Reference

[1]Saha P., Banerjee A., Bhattacharayya P. and Dandapat A., "Improved matrix multiplier design for high-speed digital signal processing applications", IET Circuits, Devices and Systems, Vol. 8, No. 1, pp. 27-37, 2014.

[2]Ozgun M.T. and Torlak M., "Effects of random delay errors in continues-time semi-digital transversal filters", IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 183-190, 2014.

[3]Tanzawa T., "An optimum design for integrated switched-capacitor Dickson charge pump multipliers with area power balance", IEEE Transactions on Power Electronics, Vol. 29, No. 2, 534-538, 2014.

[4]Ying Y. H., Lin, J. M. and Lee C. Y., "Low space-complexity digit-serial dual basis systolic multiplier over Galois field GF (2^m) using Hankel matrix and Karatsuba algorithm", IET Information Security, Vol. 7, No. 2, 75-86, 2013.

[5]Oivero A., Torresani B. and Martinet K. R., "A class of algorithms for time-frequency multiplier estimation", IEEE Transactions on Audio, Speech and Language Processing, Vol. 21, No. 8, 1550-1559, 2013.

[6]Caro D. D., Petra N., Strollo A. G. M. and Tessitore F., "Fixed-width multipliers and multipliers-accumulators with min-max approximation error", IEEE Transactions on circuits and Systems I: Regular Papers, Vol. 60, No. 9, pp. 2375-2388, 2013.

[7]Kuang S. R., Wang K. C. and Hsu H. W., "Energy-efficient high-throughput Montgomery modular multipliers for RSA cryptosystems", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, No. 11, 2013.

[8]Chen S. K., Liu C. W., Wu T. Y. and Tsai A. C., "Desiin and implementation of high-speed and energy-efficient variable-latency speculating Booth multiplier (VLSBM)", IEEE Transactions on Circuits and Systems I: regular Papers, Vol. 60, No. 10, pp. 2631-2643, 2013.

[9]Chen J. and Chang C. H., "High-level synthesis algorithm for the design of reconfigurable constant multiplier", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, No. 12, pp. 1844-1856, 2009.

[10]Yajuan H. and Chang C. H., "A new redundant binary Booth encoding for fast 2^n-bit multiplier design", IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 56, No. 6, pp. 1192-1201, 2009.

[11]Seo Y. H. and Kim D. W., "A new VLSI architecture of parallel multiplier-accumulator based on radix-2 modified Booth algorithm", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 18, No. 2, pp. 201-208, 2010.