International Journal of Information Engineering and Electronic Business(IJIEEB)

ISSN: 2074-9023 (Print), ISSN: 2074-9031 (Online)

Published By: MECS Press

IJIEEB Vol.8, No.6, Nov. 2016

Design & Optimization of Reversible Logic Based ALU Using ACO

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Shaveta Thakral, Dipali Bansal

Index Terms

Ant colony optimization;Arithmetic logic unit;Depth first search;Quantum cost;Reversible logic


Portable consumer electronics is most demanding in every segment of electronic industry and to satisfy the needs of low power electronics, comprehensive approaches and techniques have been proposed by various researchers. Reversible logic is one among emerging and competent technologies with profound applications in fields of computer graphics, optical information processing, quantum computing, DNA computing, ultra low power CMOS design and communication. ALU is a fundamental component of all processing units. Portability in computing system highly demands for reversible logic based ALU. Many researchers have proposed exact synthesis approaches of ALU design based on reversible logic but few have come up with reduced quantum cost without long computation overhead. Here in this paper heuristic approach has been used which not only provides solution for large number of variables but also avoids sufferings caused by long computation overhead. The main goal of this paper is to propose reversible logic based ALU and further it is optimized by Ant Colony Optimization (ACO) algorithm combined with Depth First Search (DFS) in terms of reduced quantum cost. 

Cite This Paper

Shaveta Thakral, Dipali Bansal,"Design & Optimization of Reversible Logic Based ALU Using ACO", International Journal of Information Engineering and Electronic Business(IJIEEB), Vol.8, No.6, pp.55-61, 2016. DOI: 10.5815/ijieeb.2016.06.07


[1]M.Li, Y. Zheng, MS. Hsiao and C. Huang, "Reversible logic synthesis through ant colony optimization," Design, Automation & Test in Europe Conference & Exhibition; 8-12 March 2010; Dresden.Europe: IEEE, pp.307-310.

[2]M. Sarkar, P. Ghosal, SP. Mohanty, "Reversible circuit synthesis using ACO and SA based quine-mcCluskey method," IEEE 2013 56th International Midwest Symposium on Circuits and Systems; 4-7 August 2013; Columbus.OH, IEEE.pp.416-419.

[3]WJ. Gutjahr,"ACO algorithm with guaranteed convergence to the optimal solution," Information Processing Letters, 82(3):145–153,2002.

[4]K. Fazel, M. A. Thornton, J. E. Rice, "ESOP-based Toffoli Gate Cascade Generation," IEEE 2007 Pacific Rim Conference on Communication, Computers and Signal Processing;,22-24 August 2007;Victoria.BC: IEEE.pp.206-209.

[5]R. Singh, S.Upadhyay, S.Saranya S, Soumya, KB.Jagannath, SA. Hariprasad,"Efficient Design of Arithmetic Logic Unit using Reversible Logic Gates," IJARCET 2014, vol. 3, pp. 1474-1477

[6]M.Matthew, L.Matthew,M. Richard and R.Nagarajan,"Design of a Novel Reversible ALU using an Enhanced Carry Look-Ahead Adder," 11th IEEE International Conference on Nanotechnology; 15-18 August 2011; Portland.Marlott:IEEE.pp.1436-1440.

[7]Z. Guan, W. Li, W. Ding, Y. Hang, L.iNi,"An arithmetic logic unit design based on reversible logic gates," Pacific Rim Conference on Communication, Computers and Signal Processing; 23-26 August 2011; Victoria.BC:IEEE.pp.925-931.

[8]Y. Syamala, A. V. N. Tilak, "Reversible arithmetic logic unit," 3rd International conference on Electronics Computer Technology(JCECT);8-10 April,2011;Kanyakumari:IEEE.pp.207-211.

[9]MB. Ali, MM. Hossin and ME> Ullah," Design of Reversible Sequential Circuit Using Reversible Logic Synthesis", International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.4, December 2011

[10]F. Sharmin, RK. Mitra, R. Hasan, A. Rahman "Low cost reversible signed comparator" International Journal of VLSI design & Communication Systems" Vol.4, No.5,pp:19- 33,2013

[11]B.Dehghan, A.Roozbeh, J. Zare "Design of low power comparator using DG gate" Scientific research ciruits and systems 7-12, 2014

[12]N. Pandey, N.Dadhich, MZ. Talha "Realization of 2-to-4 reversible decoder and its applications" International Conference on Signal Processing and Integrated Networks (SPIN) pp: 349- 353, 2014

[13]V. Oklobdzija, "High -Speed VLSI Arithmetic Units: Adders and Multipliers", in "Design of High -Performance Microprocessor Circuits", Book Chapter, Book edited by A. Chandrakasan, IEEE Press, 2000.

[14]M. K. Thomson, Robert Gluck and Holger Bock Axelsen,"Reversible arithmetic logic unit for quantum arithmetic", Journal of Physics A: Mathematical and Theoretical. Vol.43, 2010.

[15]Towards a Design Flow for Reversible Logic -Robert Wille and RolphDrechsler, ISBN: 978-90-481-9578-7 Springer Dordrecht Heidelberg London New York