INFORMATION CHANGE THE WORLD

International Journal of Image, Graphics and Signal Processing(IJIGSP)

ISSN: 2074-9074 (Print), ISSN: 2074-9082 (Online)

Published By: MECS Press

IJIGSP Vol.5, No.8, Jun. 2013

Bit Serial Architecture for Variable Block Size Motion Estimation

Full Text (PDF, 712KB), PP.63-69


Views:96   Downloads:1

Author(s)

Krishna Kaveri Devarinti,T.Sai Lokesh,Gangadhar Vukkesala

Index Terms

Motion estimation, H.264, SAD, Macroblock, PE, Bit serial, variable block size, MV

Abstract

H.264/AVC is the latest video coding standard adopting variable block size, quarter-pixel accuracy and motion vector prediction and multi-reference frames for motion estimations. These new features result in higher computation requirements than that for previous coding standards.The computational complexity of motion estimation is about 60% in the H.264/AVC encoder. In this paper most significant bit (MSB first) arithmetic based bit serial Variable Block Size Motion Estimation (VBSME) hardware architecture is proposed. MSB first bit serial architecture main feature is, its early termination SAD computation compared to normal bit serial architectures. With this early termination technique, number computations are reduced drastically. Hence power consumption is also less compared to parallel architectures. An efficient bit serial processing element is proposed and developed 2D architecture for processing of 4x4 block in parallel .Inter connect structure is developed in such way that data reusability is achieved between PEs. Two types of adder trees are employed for variable block size SAD calculation with less number of adders. The proposed architecture can generate up to 41 motion vectors (MVs) for each macroblock. The inter connection complexity between PEs reduced drastically compared to parallel architectures. The architecture supports processing of SDTV (640x480) with 30fps at 172.8 MHz for search range [+8, -7]. We could reduce 14% of computations by using early termination technique. 

Cite This Paper

Krishna Kaveri Devarinti,T.Sai Lokesh,Gangadhar Vukkesala,"Bit Serial Architecture for Variable Block Size Motion Estimation", IJIGSP, vol.5, no.8, pp.63-69, 2013.DOI: 10.5815/ijigsp.2013.08.08

Reference

[1]Wiegand, T., Sullivan, G. J., Bjontegaard, G., & Luthra, A. (2003). Overview of the H.264/AVC video coding standard. IEEE Transactions on Circuits and Systems for Video Technology, 13(7), 560–576. 

[2]Kim, M., Hwang, I., & Chae, S. I. (2005). A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264. In Proc. ASP-DAC (Vol. 1, pp. 631– 634).

[3]Yap, S. Y., & McCanny, J. V. (2004). A VLSI architecture for variable block size video motion estimation. IEEE Transactions on CAS II, 51(7), 384–389.

[4]Ou, C.-M., Le, C.-F., & Hwang, W.-J. (2005). An efficient VLSI architecture for H.264 variable block size motion estimation. IEEE Transaction on Consumer Electronics, 51(4), 1291–1299.

[5]Yap, S. Y., & McCanny, J. V. (2003). A VLSI architecture for advanced video coding motion estimation. In Proc. IEEE intl. conf. applications-specif ic systems, arch., processors (pp. 293–301).

[6]C. L. Su and C. W. Jen. Motion Estimation using MSD-first Processing. In Proc. of IEEE circuits, device and and systems, volume 150, pages 124–133, Apr. 2003.

[7]H. Loukil, F. Ghozzi, and A. Samet. Hardware implementation of Block Matching Algorithm with FPGA technology. In IEEE Int. Conf. on Microelectronics, volume 16, pages 542–546, 2004. 

[8]M. Mohammadzadeh, M. Eshghi, and M. Azadfar. An Optimized Systolic Array Architecture for Full Search Block Matching Algorithm and its Implementation on FPGA chips. In IEEE Int. Conf. NEWCAS, volume 3, pages 327– 330, 2005.

[9]S.Wong, S. Vassiliadis, and S. Cotofana. A Sum of Absolute Differences Implementation in FPGA Hardware. In Proc. of 28th Euromico Conf., pages 183–188, Sept. 2002.

[10]C.Wei and M. Z. Gang. A novel SAD Computing Hardware Architecture for Variable-size Block Matching Estimation and Its Implementation with FPGA. In Proc. of IEEE Int. Symp. on Circuits and Systems, volume 1, pages 683–686, 2000.

[11]S. Lopez, F. Tobajas, A. Villar, V. de Armas, J. Lopez, and R. Sarmiento. Low Cost Efficient Architecture for H.264 Motion Estimation. In Proc. of IEEE Int. Symp. on Circuits and Systems, volume 1, pages 412–415, 2005.