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International Journal of Intelligent Systems and Applications(IJISA)

ISSN: 2074-904X (Print), ISSN: 2074-9058 (Online)

Published By: MECS Press

IJISA Vol.4, No.4, Apr. 2012

Design of Fast Pipelined Multiplier using Modified Redundant Adder

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Author(s)

Rakesh Kumar Saxena, Neelam Sharma, A. K Wadhwani

Index Terms

Signed Digit;Fast Multiplier;Fast Computing;High-speed arithmetic;Pipelining

Abstract

Carry free arithmetic using higher radix number system such as Redundant Binary Signed Digit can be used to meet the demand for computers operating at much higher speeds. The computation speed can also be increased by using the suitable design of adder and multiplier circuits. Fast RBSD adder cells suggested by Neelam Sharma in 2006 using universal logic are modified in the proposed design by reducing the number of gates. Due to reduction in gate count, number of gate levels and hence the circuit complexity is also reduced. As multiplication is repetitive addition, the implementation time of the multiplier circuit will also be reduced to a great extent by using modified design of adder cell to add the partial products. These partial products are added using pipelined units to reduce implementation time further. Thus with the use of proposed RBSD adder, other arithmetic operations such as subtraction, division, square root etc. can be performed much faster. It is concluded that efficiency of the proposed RBSD adder and multiplier is improved as compared to the techniques conventionally used in high speed machines. Thus the proposed modified RBSD adder cell using universal gates can be used to design fast ALU with many additional advantages.

Cite This Paper

Rakesh Kumar Saxena, Neelam Sharma, A. K Wadhwani,"Design of Fast Pipelined Multiplier using Modified Redundant Adder", International Journal of Intelligent Systems and Applications(IJISA), vol.4, no.4, pp.47-53, 2012. DOI: 10.5815/ijisa.2012.04.07

Reference

[1]Avizienis A., “Signed digit number representation for fast parallel arithmetic,” IRE Trans. Electron Computers., vol EC-10, pp.389-400, 1961.

[2]Hwang K., “Computer Arithmetic/Principles, Architecture and Design,” New York: Wiley, 1979.

[3]Chow C. Y. and Robertson J. E., “Logical Design of a Redundant Binary Adder,” In Proc. of 4th Symposium on Computer Arithmetic, pp. 109-115, 1978.

[4]Rakesh Kumar Saxena, Neelam Sharma and A. K. wadhwani, “Novel Design of Fast RBSD Adder with Reduced NOR-NOR Logic”, International Journal of Computer and Network Security(IJCNS), vol. 2, no. 7, pp 52-56 (2010).

[5]Neelam Sharma., “Development of Fast RBSD Arithmetic Logic Unit”, Ph.D Thesis, U. P. Technical University, Lucknow, India, 2006.

[6]A. D. Booth.. “A Signed Binary Multiplication Technique,” J . mech. appl. math: 4, Oxford University Press, pp. 236-240, 1951.

[7]Chen, I Shi E. and Rajashekhara, T.N., “A fast multiplier Design Using Singed Digit Numbers and 3-Valved Logic,” In proc. of IEEE, Binngamton New York, 1991.

[8]Besli, N. and Deshmukh, R.G., “A novel Redundant Binary Signed–Digit (RBSD) Booth’s Encoding,” In proc. of IEEE, Southeastcon, 2002.

[9]Dadda L. and Piuri V., “Pipelined Adders,” IEEE Transactions on Computers, vol. 45, No. 3, pp. 348-356, 1996.

[10]Hallin, T. G. and Flynn M. J., “Pipelining of Arithmetic Functions”, IEEE Transactions of computers, pp. 880-885, 1972.

[11]Rajashekhar, T.N.and Kal, O., “Fast Multiplier Design using Redundant Signed- Digit Numbers”, International Journal of Electronics, vol.69, no. 3, pp –359-368, 1990.

[12]Gloria A. D. and Olivieri M., “Statistical Carry Look-ahead Adders,” IEEE Transactions on Computers, vol. 45, No. 3, pp. 340-356, 1996.

[13]Cortadella J. and Lang T., “High Radix Division and Square – Root with Speculation,” IEEE Transactions on Computer, vol. 43, no. 8, pp. 919-931, 1994.

[14]Jump J. R. and Ahuja S. R., “Effective Pipelining of Digital System,” IEEE Transaction on computers, vol. C-27, no. 9, pp. 855-865, 1978. 

[15]Cotolora, S. and Vassiliadis, S. (2000). “Signed Digit Addition and Related Operations with Threshold Logic,” IEEE Transaction on Computers, vol. 49, no. 3, 2000.

[16]M D Ercegovac, J M Muller, Tisseran., “Reciprocation, Square root, Inverse Square root and some Elementary functions using small Multipliers”, IEEE Transactions on computers, vol 49, no. 7, July 2000. 

[17]Parhami B, “Carry free Addition of Recorded Binary Signed-Digit Numbers,” IEEE Transactions on computers, vol. 37 no. 11, pp. 1470-1476 ,1988.

[18]Rajashekhar, T.N. and I-Shi Eric Chen., “A Fast Adder Design Using Signed-Digit Numbers and Ternary Logic,” In proc. IEEE Southern Tier Technical Conference, Binngamton, New York, pp.187-194, 1990.