INFORMATION CHANGE THE WORLD

International Journal of Intelligent Systems and Applications(IJISA)

ISSN: 2074-904X (Print), ISSN: 2074-9058 (Online)

Published By: MECS Press

IJISA Vol.4, No.5, May. 2012

Analysis and Design of Tri-Gate MOSFET with High Dielectrics Gate

Full Text (PDF, 487KB), PP.16-22


Views:111   Downloads:2

Author(s)

Viranjay M. Srivastava, Setu P. Singh

Index Terms

Tri-gate MOSFET;Radio frequency;HfO_2;High dielectric constant;CMOS;VLSI

Abstract

The scaling of simple gate transistors requires the scaling and transistor elements like source/drain junction became difficult to scale further after a limit due to adverse effect of electrostatic and short-channel performance. The solution of the problem is tri-gate where we can increase the performance without increasing the width and without scaling. In this paper we have described the parameter of tri-gate and taking the high dielectric as substrate.

Cite This Paper

Viranjay M. Srivastava, Setu P. Singh,"Analysis and Design of Tri-Gate MOSFET with High Dielectrics Gate", International Journal of Intelligent Systems and Applications(IJISA), vol.4, no.5, pp.16-22, 2012. DOI: 10.5815/ijisa.2012.05.03

Reference

[1]R. Chau, B. Doyle, J. Kavalieros, D. Barlage, A. Murthy, M. Doczy, R. Arghavani, and S. Datta, “Advanced depleted-substrate transistors: single-gate, double-gate, and tri-gate,” Proc. of Int. Conf. on Solid-State Devices and Materials, Japan, 2002, pp. 68-69.

[2]J. Kavalieros, B. Doyle, W. Rachmady, M. Radosavljevic, N. Zelick, and R. Chau, “Tri-gate transistor architecture with high-k gate dielectrics, metal gates, and strain engineering,” Prog. of Symp. on VLSI Technology, Digest of Technical Papers, June 2006, pp. 62-63.

[3]J. M. Sallese, N. Chevillon, B. Iniguez, and F. Pregaldiny, “Charge based modeling of junctionless double-gate field-effect transistors,” IEEE Trans. on Electron Devices, vol. 58, no. 8, pp. 2628-2637, Aug. 2011.

[4]Viranjay M. Srivastava, K. S. Yadav, and G. Singh, “Design and performance analysis of double-gate MOSFET over single-gate MOSFET for RF switch,” Microelectronics Journal, vol. 42, no. 3, pp. 527-534, March 2011.

[5]N. Mohan kumar, B. Syamal, J. Shamshudeen, K. Vijayan, R. Saravanakumar, S. Baskaran, K. Bharath, and C. K. Sarkar, “Noise performance of gate engineered double gate MOSFETs for analog and RF applications,” Proc. of Int. Conf. on Electrical and Computer Engineering (ICECE-2010), India, 18-20 Dec. 2010, pp. 586 – 589.

[6]Electronic archive of new semiconductor materials, characteristics and properties, Loffe Physico technical Institute, Russian Federation, St. Petersburg, 2010.

[7]Bo Yu , Huaxin Lu, Minjian Liu, and Yuan Taur, “Explicit continuous models for double-gate and surrounding-gate MOSFETs,” IEEE Trans. on Electron Devices, vol. 54, no. 10, pp. 2715-2722, Oct. 2007.

[8]Viranjay M. Srivastava, K. S. Yadav, and G. Singh, “Design and performance analysis of cylindrical surrounding double-gate MOSFET for RF switch,” Microelectronics Journal, vol. 42, no. 10, pp. 1124-1135, Oct. 2011.

[9]Xin Sun, Qiang Lu, V. Moroz, H. Takeuchi, G. Gebara, and J. Wetzel, “Tri-gate bulk MOSFET design for CMOS scaling to the end of the roadmap,” IEEE Electron Device Letters, vol. 29, no. 5, pp. 491-493, May 2008.

[10]F. Lime, and B. Guillaumot, “Investigation of electron and hole mobilities in MOSFETs with TiN/HfO2/SiO2 gate stack,” Proc. of 33rd Int. Conf. on European Solid State Device Research, 16-18 Sept. 2003, pp. 247-250.

[11]S. Kubicek, J. Chen, A. Ragnarsson, R. J. Carter, V. Kaushik, and K. De Meyer, “Investigation of poly-Si/HfO/sub 2/gate stacks in a self-aligned 70 nm MOS process flow,” Proc. of 33rd Int. Conf. on European Solid-State Device Research, 16-18 Sept. 2003, pp. 251-254.

[12]B. Doyle, B. Boyanov, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, R. Rios, and R. Chau, “Tri-gate fully-depleted CMOS transistors: fabrication, design and layout,” Proc. of Symp. on VLSI Technology, Digest of Technical Papers, 10-12 June 2003, pp. 133-134.

[13]M. Saitoh, Y. Nakabayashi, K. Ota, K. Uchida, and T. Numata, “Performance improvement by stress memorization technique in trigate silicon nanowire MOSFETs,” IEEE Electron Device Letters, vol. 33, no. 3, pp. 8-10, Jan. 2012.

[14]Viranjay M. Srivastava, K. S. Yadav, and G. Singh, “Possibilities of HfO2 for double-pole four-throw double-gate RF CMOS switch,” Proc. of IEEE 2011 Int. Symp. on Microwave, Antenna, Propagation and EMC Technologies for Wireless Communications (MAPE-2011), China, 1-3 Nov. 2011, pp. 309-312.

[15]N. P. Maity, A. Pandey, S. Chakraborty and M. Roy, “High-k HfO2 Based Metal-Oxide-Semiconductor Devices Using Silicon and Silicon Carbide Semiconductor,” J. of Nano Electronics Physics, vol. 3, no. 1, pp. 947-955, 2011.

[16]Viranjay M. Srivastava, K. S. Yadav, and G. Singh, “Analysis of double gate CMOS for double-pole four-throw RF switch design at 45-nm technology,” J. of Computational Electronics, vol. 10, no. 1-2, pp. 229-240, June 2011.