International Journal of Information Technology and Computer Science(IJITCS)
ISSN: 2074-9007 (Print), ISSN: 2074-9015 (Online)
Published By: MECS Press
IJITCS Vol.5, No.8, Jul. 2013
A Comparative Performance Analysis of Low Power Bypassing Array Multipliers
Full Text (PDF, 496KB), PP.38-45
Low power design of VLSI circuits has been identified as vital technology in battery powered portable electronic devices and signal processing applications such as Digital Signal Processors (DSP). Multiplier has an important role in the DSPs. Without degrading the performance of the processor, low power parallel multipliers are needed to be design. Bypassing is the widely used technique in the DSPs when the input operand of the multiplier is zero. A Row based Bypassing Multiplier with compressor at the final addition of the ripple carry adder (RCA) is designed to focus on low power and high speed. The proposed bypassing multiplier with compressor shows high performance and energy efficiency than Kuo multiplier with Carry Save Adder (CSA) at the final RCA.
Cite This Paper
Nirlakalla Ravi, S. Venkateswarlu, T. Jayachandra Prasad, Thota Subba Rao,"A Comparative Performance Analysis of Low Power Bypassing Array Multipliers", International Journal of Information Technology and Computer Science(IJITCS) vol.5, no.8, pp.38-45, 2013. DOI: 10.5815/ijitcs.2013.08.04
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