International Journal of Information Engineering and Electronic Business (IJIEEB)
IJIEEB Vol. 10, No. 4, 8 Jul. 2018
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Area & Power Optimization of Asynchronous Processor Using Xilinx ISE & Vivado
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Author(s)
Archana Rani
1,*
Naresh Grover
1
Index Terms
FPGA, Microprocessor design, Optimiza-tion, Xilinx Synthesis Tool (XST) and Vivado
Abstract
As the technology era has been changing, the designing pattern of an IC is also changing. An IC de-signing is now divided into two definite fields i.e. Front-End design and Back-End design. The Front-End design is using HDLs (Hardware Description Languages i.e. VHDL or Verilog) and the verification of those ICs, whereas the Back-End Design is related to the Physical Design techniques. But both of the IC design techniques required some extra efforts in terms of their Speed, Shape, and Size, which needs the Optimization efforts. This pa-per deals with the area and power optimization efforts in terms of the logic utilization by using XST & Vivado Tools. After applying area optimization techniques i.e. Logic Optimization, LUT mapping and Resource Sharing etc. on already designed asynchronous microprocessor to be used as model for proposed optimization, reasonable results in terms of power and area utilization have been achieved.
Cite This Paper
Archana rani, Naresh Grover, "Area & Power Optimization of Asynchronous Processor Using Xilinx ISE & Vivado", International Journal of Information Engineering and Electronic Business(IJIEEB), Vol.10, No.4, pp. 8-15, 2018. DOI:10.5815/ijieeb.2018.04.02
Reference
[1]Matthew French, Li Wang, Tyler Anderson, Michael Wirthlin “Post Synthesis Level Power Modeling of FPGAs” Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’05) 2005 IEEE.
[2]Maico Cassel, Fernanda Lima Kastensmidt “Evaluating One-Hot Encoding Finite State Machines for SEU Reliability in SRAM-based FPGAs” Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS'06)
[3]Jason Cong Bin Liu, Stephen Neuendorffer, Juanjo Noguera, Kees Vissers, and Zhiru Zhang “IEEE Transactions On Computer-Aided Design Of Integrated Circuits And Systems, VOL. 30, NO. 4, April 2011.
[4]B.G. Kim, and D.L. Dietmeyer, "Multilevel logic synthesis of symmetric switching functions," IEEE Trans. on CAD, Vol. 10, No. 4, pp. 436-446, April 1991.
[5]L. Yan, T. Srikanthan, and N. Gang, “Area and Delay Estimation for FPGA Implementation of Coarse-Grained Reconfigurable Architectures,” LCTES, Ottawa, Ontario, Canada,pp.182–188, 2006.
[6]D. Kulkarni, Walid A. Najjar, R. Rinker and F. J. Kurdahi,“Compile-Time Area Estimation for LUT-Based FPGAs,” ACMTODAES, Vol. 11, No. 1, pp. 104–122, 2006.
[7]A. Mishchenko, S. Chatterjee, R. K. Brayton, “Improvements to Technology Mapping for LUT–Based FPGAs,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 2, pp. 240–253, Feb. 2007.
[8]D. Chen, J. Cong, Y. Fan, and Z. Zhang, “High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs,”ASPDAC’0, Yokohama, Japan, pp. 529-534, 2007.
[9]Pablo González de Aledo Marugán, Javier González-Bayón and Pablo Sánchez Espeso, “Hardware performance estimation by Dynamic Scheduling” ;in Proc. FDL, 2011, pp.1-6.
[10]Michael Kunz, Martin Kumm, Martin Heide, Peter Zipf, “Area Estimation of Look-Up Table Based Fixed-Point Computations on the example of a Real-Time High Dynamic Range Imaging System" In 22nd International conference on Field Programmable Logic and Applications(FPL), pages 591-594, Aug 29-31 2012.
[11]A. M. Smith, G. A. Constantinides, and P. Y. K. Cheung, “Integrated floorplanning, module-selection, and architecture generation for reconfigurable devices,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 6, pp. 733–744, Jun 2008.
[12]J. Luu, I. Kuon, P. Jamieson, T. Campbell, A. Ye, M. Fang, and J. Rose, “Vpr 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling,” in Int’l Symp. on Field-Programmable Gate Arrays, Feb. 2009, pp. 133–142.
[13]E. Ahmed and J. Rose, “The effect of LUT and cluster size on deep-submicron FPGA performance and density,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 3, pp. 288–298, Mar. 2004.
[14]H. Q. Dao, B. R. Zeydel, V. G. Oklobdzija: "Energy minimization method for optimal energy-delay extraction" Proceedings of European Solid-State Circuits Conference, p. 177-180, 2003.
[15]Naresh Grover, M.K.Soni,” Simulation and Optimization of VHDL code for FPGA-Based Design using Simulink” I.J. Information Engineering and Electronic Business, 2014, 3, 22-27.