International Journal of Information Engineering and Electronic Business (IJIEEB)
IJIEEB Vol. 6, No. 1, 8 Feb. 2014
Cover page and Table of Contents: PDF (size: 703KB)
Design of FPGA based 32-bit Floating Point Arithmetic Unit and verification of its VHDL code using MATLAB
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Author(s)
Naresh Grover
1,*
M.K.Soni
1
Index Terms
Floating Point, Arithmetic Unit, VHDL, Modelsim, Simulink
Abstract
Most of the algorithms implemented in FPGAs used to be fixed-point. Floating-point operations are useful for computations involving large dynamic range, but they require significantly more resources than integer operations. With the current trends in system requirements and available FPGAs, floating-point implementations are becoming more common and designers are increasingly taking advantage of FPGAs as a platform for floating-point implementations. The rapid advance in Field-Programmable Gate Array (FPGA) technology makes such devices increasingly attractive for implementing floating-point arithmetic. Compared to Application Specific Integrated Circuits, FPGAs offer reduced development time and costs. Moreover, their flexibility enables field upgrade and adaptation of hardware to run-time conditions. A 32 bit floating point arithmetic unit with IEEE 754 Standard has been designed using VHDL code and all operations of addition, subtraction, multiplication and division are tested on Xilinx. Thereafter, Simulink model in MAT lab has been created for verification of VHDL code of that Floating Point Arithmetic Unit in Modelsim.
Cite This Paper
Naresh Grover, M.K.Soni, "Design of FPGA based 32-bit Floating Point Arithmetic Unit and verification of its VHDL code using MATLAB", International Journal of Information Engineering and Electronic Business(IJIEEB), vol.6, no.1, pp.1-14, 2014. DOI:10.5815/ijieeb.2014.01.01
Reference
[1]N. Shirazi, A. Walters, and P. Athanas, "Quantitative analysis of floating point arithmetic on fpga based custom computing machines," in Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, pp. 155–162, 1995.
[2]P. Belanovic and M. Leeser, "A library of parameterized floating-point modules and their use,"in Proceedings of the International Conference on Field Programmable Logic and Applications, 2002.
[3]J. Dido, N. Geraudie, L. Loiseau, O. Payeur, Y. Savaria, and D. Poirier, "A flexible floating-point format for optimizing data-paths and operators in fpga based dsps," in Proceedings of the ACM International Symposium on Field Programmable Gate Arrays, (Monterrey, CA), February 2002.
[4]A. A. Gaar, W. Luk, P. Y. Cheung, N. Shirazi, and J. Hwang, "Automating customisation of floating-point designs," in Proceedings of the International Conference on Field Programmable Logic and Applications, 2002.
[5]J. Liang, R. Tessier, and O. Mencer, "Floating point unit generation and evaluation for fpgas," in Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, (Napa Valley, CA), pp. 185–194, April 2003.
[6]IEEE Standards Board, "IEEE standard for binary floating-point arithmetic," Tech. Rep. ANSI/IEEE Std. 754-1985, The Institute of Electrical and Electronics Engineers, New York, 1985.
[7]B.Fagin and C. Renard, "Field programmable gate arrays and floating point arithmetic," IEEE Transactions on VLSI, vol. 2, no. 3, pp. 365–367, 1994.
[8]W. B. Ligon, S. P. McMillan, G. Monn, F. Stivers, K. Schoonover, and K. D. Underwood, "A re-evaluation of the praticality of floating-point on FPGAs," in Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, (Napa Valley, CA), pp. 206–215, April 1998.
[9]Z. Luo and M. Martonosi, "Accelerating pipelined integer and floating-point accumulations in configurable hardware with delayed addition techniques," IEEE Transactions on Computers, vol. 49, no. 3, pp. 208–218, 2000.
[10]X. Wang and B. E. Nelson, "Tradeoffs of designing floating-point division and square root on virtex fpgas," in Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, (Napa Valley, CA), pp. 195–203, April 2003.
[11]IEEE 754-2008, IEEE Standard for Floating-Point Arithmetic, 2008.
[12]Simulink HDL Coder 1; User's Guide; 2006-2010 by the MathWorks, Inc.
[13]Hikmat N. Abdullah and Hussein A. Hadi "Design and Implementation of FPGA Based Software Defined Radio Using Simulink HDL Coder". Engineering and Technology Journal, Iraq, ISSN 1681-6900 01/2010; Vol.28 (No.23):pp.6750-6767.
[14]B. K. Mishra, S. Save , R. Mane. A frame work for model based designing of analog circuits using Simulink. ICWET '11 Proceedings of the International Conference & Workshop on Emerging Trends in Technology. Pages 1225-1228; ACM New York, NY, USA ?2011 ISBN: 978-1-4503-0449-8.
[15]Alejandro A. Valenzuela, Hikmat N. Abdullah. A Joint Matlab/FPGA Design of AM Receiver for Teaching Purposes. Electromagnetics and Network Theory and their Microwave Technology Applications , 2011, pp 189-199.