International Journal of Intelligent Systems and Applications (IJISA)
IJISA Vol. 15, No. 3, 8 Jun. 2023
Cover page and Table of Contents: PDF (size: 276KB)
Static Timing Analysis of Different SRAM Controllers
Full Text (PDF, 276KB), PP.33-43
Views: 0 Downloads: 0
Author(s)
Index Terms
Slack, Static Timing Analysis (STA), Clock Skew, Register Transfer Level (RTL), SRAM Controllers
Abstract
Timing-critical path analysis is one of the most significant terms for the VLSI designer. For the formal verification of any kinds of digital chip, static timing analysis (STA) plays a vital role to check the potentiality and viability of the design procedures. This indicates the timing status between setup and holding times required with respect to the active edge of the clock. STA can also be used to identify time sensitive paths, simulate path delays, and assess Register transfer level (RTL) dependability. Four types of Static Random Access Memory (SRAM) controllers in this paper are used to handle with the complexities of digital circuit timing analysis at the logic level. Different STA parameters such as slack, clock skew, data latency, and multiple clock frequencies are investigated here in their node-to-node path analysis for diverse SRAM controllers. Using phase lock loop (ALTPLL), single clock and dual clock are used to get the response of these controllers. For four SRAM controllers, the timing analysis shows that no data violation exists for single and dual clock with 50 MHz and 100 MHz frequencies. Result also shows that the slack for 100MHz is greater than that of 50MHz. Moreover, the clock skew value in our proposed design is lower than in the other three controllers because number of paths, number of states are reduced, and the slack value is higher than in 1st and 2nd controllers. In timing path analysis, slack time determines that the design is working at the desired frequency. Although 100MHz is faster than 50MHz, our proposed SRAM controller meets the timing requirements for 100MHz including the reduction of node to node data delay. Due to this reason, the proposed controller performs well compared to others in terms slack and clock skew.
Cite This Paper
Jabin Sultana, S. M. Shamsul Alam, "Static Timing Analysis of Different SRAM Controllers", International Journal of Intelligent Systems and Applications(IJISA), Vol.15, No.3, pp.33-43, 2023. DOI:10.5815/ijisa.2023.03.03
Reference
[1]A. Kumar, S. L. Tripathi, S. Dhariwal, “Static timing analysis of sequential circuit with GUI”, 2020 IEEE International Women in Engineering (WIE) Conference on Electrical and Computer Engineering (WIECON-ECE), IEEE, 2020, pp. 312-315
[2]P. P. Chu, FPGA prototyping by Verilog examples: Xilinx Spartan-3 version, John Wiley & Sons, 2011.
[3]J. Sultana, S. M. S. Alam, “Performance analysis and implementation of sram controller on altera de2 board”, In: 2021 International Conference on Electronics, Communications and Information Technology (ICECIT), 2021, pp. 1–4. doi:10.1109/ICECIT54077.2021.9641430.
[4]E. Salman, A. Dasdan, F. Taraporevala, K. Kucukcakar, E. G. Friedman, “Exploiting setup–hold-time interdependence in static timing analysis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems vol.26 (6) (2007) pp. 1114–1125.
[5]R. Abdollahi, K. Hadidi, A. Khoei, A simple and reliable system to detect and correct setup/hold time violations in digital circuits, IEEE Transactions on Circuits and Systems I: Regular Papers vol. 63 (10) (2016) pp.1682–1689.
[6]IS65WV102416BLL SRAM datasheet pdf, www.issi.com, accessed: 2022-5-16.
[7]ALTPLL (phase-locked loop) IP core user guide, https://www.intel.com/programmable/technical-pdfs/683732.pdf
[8]M. Thakur, B. B. Soni, P. Gaur, P. Yadav, Analysis of metastability performance in digital circuits on flip-flop, In 2014 International Conference on Communication and Network Technologies, IEEE, 2014, pp. 265–269.
[9]Chapter2 clocks resets-04, https://rb.gy/hvnryq.
[10]J. Bhasker, Rakesh Chadha, “Static Timing Analysis for Nanometer Designs a Practical Approach” Springer, 2009th edition, 2011.
[11]C. XIANG, "Design and implementation of Asynchronous SRAM," 2009.
[12]Lei Li, Jianhao Hu, Chun He and Wanting Zhou, "Statistical clock skew modeling and analysis for resonant clock distribution networks," International Conference on Communications, Circuits and Systems 2009, pp. 1024-1028, doi: 10.1109/ICCCAS.2009.5250335, 2009.
[13]Altera DE2-115 User Manual, available on https://www.intel.com. [Accessed: 12-Mar-2022].
[14]“Minimum pulse width,” Blogspot.com. [Online]. Available: https://vlsiuniverse.blogspot.com/2016/09/min-pulse-width-check.html. [Accessed: 07-Mar-2021].
[15]J. Mistry, “VLSI Basic,” Blogspot.com. [Online]. Available: https://vlsibasic.blogspot.com/2014/10/clock-skew.html. [Accessed: 07-Mar-2022].