International Journal of Information Technology and Computer Science (IJITCS)
IJITCS Vol. 10, No. 12, 8 Dec. 2018
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Low Power and Area Optimized Architectures for BPSK Modulator
Full Text (PDF, 843KB), PP.33-40
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Author(s)
Usha S.M.
1,*
Mahesh H.B.
2
Index Terms
BPSK, QPSK, BOOTH MULTIPLIER, RTL, Cadence, CMOS, BER, Costas Loop
Abstract
Low power modulators are most efficient for wireless communication. The conventional BPSK modulator consumes more power and area. In this work, the new approaches for BPSK modulator are discussed and recorded. The four new approaches consume less area and power than the conventional design of BPSK Modulator. The power and area consumed by new approaches are compared with the conventional method. Cadence software is used for the simulation and synthesis, the power and area reduction in 180nm, 90nm and 45nm CMOS Technology is reported, MATLAB/SIMULINK is used to do BER analysis of BPSK modulator with AWGN channel. The new architectures enhance the performance of BPSK Modulator in consuming less power and utilizing less area than the conventional design.
Cite This Paper
Usha S.M., Mahesh H.B., "Low Power and Area Optimized Architectures for BPSK Modulator", International Journal of Information Technology and Computer Science(IJITCS), Vol.10, No.12, pp.33-40, 2018. DOI:10.5815/ijitcs.2018.12.05
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