INFORMATION CHANGE THE WORLD

International Journal of Information Technology and Computer Science(IJITCS)

ISSN: 2074-9007 (Print), ISSN: 2074-9015 (Online)

Published By: MECS Press

IJITCS Vol.3, No.3, Jun. 2011

FPGA Based High Accuracy Synchronous Acquisition Design for Binocular Vision System

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Author(s)

Lili Lin,Wenhui Zhou

Index Terms

Binocular Stereo Vision, Synchronous Acquisition, Ping-pong Buffer, FPGA

Abstract

This paper proposes a coarse-to-fine two-level synchronous data acquisition and transmission system for binocular stereo vision, which satisfies strict synchronous requirement of stereo vision. Specifically, this synchronization system design contains: coarse level synchronous based on hardware circuit design and the fine level synchronous based on hardware description language (HDL) design. The former includes the synchronization design of clock and external trigger. The latter utilizes a multi-level synchronous control strategy from field-level to pixel-level, which consists of field-synchronous acquisition of the two-channel video inputs, two-channel Ping-pong buffers switch control module, and pixel-synchronous bit-splicing and PCI transmission module. The experiments of synchronous acquisition and display demonstrate the high reliability and great performance of this synchronous system.

Cite This Paper

Lili Lin, Wenhui Zhou, "FPGA Based High Accuracy Synchronous Acquisition Design for Binocular Vision System", International Journal of Information Technology and Computer Science(IJITCS), vol.3, no.3, pp.22-28, 2011. DOI: 10.5815/ijitcs.2011.03.04

Reference

[1]O. Schreer, C. Fehn, N. Atzpadin, etc. “A Flexible 3D TV System for Different Multi-Baseline Geometries,” IEEE International Conference on Multimedia and Expo, 1877-1880, 2006 

[2]P. Zemcik, “Hardware acceleration of graphics and imaging algorithms using FPGAs,” 18th Spring Conference on Computer Graphics, pp.25-32, 2002.

[3]D. Chaikalis, N.P. Sgouros and D. Maroulis. “A real-time FPGA architecture for 3D reconstruction from integral images,” Journal of Visual Communication and Image Representation, vol. 21, no. 1, pp. 9-16, 2010

[4]Wen-Chung Chang, Shu-An Lee. “Real-time feature-based 3D map reconstruction for stereo visual guidance and control of mobile robots in indoor environments,” IEEE International Conference on Systems, Man and Cybernetics, vol. 6, no.7, pp. 5386-5391, 2004.

[5]M.Z. Brown., D. Burschka and G..D. Hager, “Advances in computational stereo,” IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 25, no. 8, pp. 993-1008, 2003.

[6]S. Wong, S. Vassiliadis and S. Cotofana. “A sum of absolute differences implementation in FPGA hardware,” the 28th EUROMICRO Conference, Dortmund, Germany, pp.183-188, 2002

[7]Wenhui Zhou, Xin Du, Xiuqing Ye. “FPGA based binocular stereo vision system (in Chinese),” Journal of Image and Graphic, vol. 10, no.9, pp. 1166-1170, 2005.

[8]Min Ye, Wenhui Zhou, Weikang Gu. “FPGA based real-tim image filter and edge detection (in Chinese),” Chinese Journal of Sensors and Actuators, vol. 20, no. 3, pp. 623-627, 2007.

[9]NXP Semiconductors. SAA7115: PAL/NTSC/SECAM video decoder with Adaptive PAL/NTSC Comb Filter, High Performance Scaler, I2C Sliced Data Readback and SQ Pixel Output. 2002

[10]Altera Corporation. Stratix Device Handbook, Volume 1 & 2. Version 3.5. June 2006

[11]PLX Technology. PCI 9054 Date Book. Version 2.1. January 2000.