International Journal of Information Technology and Computer Science (IJITCS)
IJITCS Vol. 9, No. 2, 8 Feb. 2017
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Novel Optimized Designs for QCA Serial Adders
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Author(s)
A. Mostafaee
1,*
A. Rezaei
2
Index Terms
Quantum-dot cellular automata, QCA cell, Serial adder, QCADesigner, D flip-flop
Abstract
Quantum-dot Cellular Automata (QCA) is a new and efficient technology to implement logic Gates and digital circuits at the nanoscale range. In comparison with the conventional CMOS technology, QCA has many attractive features such as: low-power, extremely dense and high speed structures. Adders are the most important part of an arithmetic logic unit (ALU). In this paper, four optimized designs of QCA serial adders are presented. One of the proposed designs is optimized in terms of the number of cells, area and delay without any wire crossing methods. Also, two new designs of QCA serial adders and a QCA layout equivalent to the internal circuit of TM4006 IC are presented. QCADesigner software is used to simulate the proposed designs. Finally, the proposed QCA designs are compared with the previous QCA, CNTFET-based and CMOS technologies.
Cite This Paper
A. Mostafaee, A. Rezaei, "Novel Optimized Designs for QCA Serial Adders", International Journal of Information Technology and Computer Science(IJITCS), Vol.9, No.2, pp.38-46, 2017. DOI:10.5815/ijitcs.2017.02.05
Reference
[1]G.E., Moore, “Cramming more components onto integrated circuits”, Electronics, vol. 38, no. 8, pp. 114, 1965.
[2]R. Robert, “Moore's law: past, present and future”, Spectrum, IEEE, vol. 34, no. 6, pp. 52-59, 1997.
[3]International Technology Roadmap for Semiconductors, Jointly Sponsored by European Semi-conductor Industry ASSC, Japan Electronics and Information Technology Industry ASSC, 2016.
[4]C.S. Lent, P.D. Taugaw, W. Porod, “Quantum Cellular Automata,” Iopscience, vol. 4, no. 1, pp. 175-245, 1993.
[5]R. Compano, L. Molenkamp, D.J. Paul, “Technology Roadmap for Nanoelectronics,” Proceeding of the European Commission IST Programme, Future and Emerging Technologies, Conference, 1999.
[6]C.S. Lent, P.D. Taugaw, W. Porod, “Bistable saturation in coupled quantum dots for quantum cellular automata,” Applied Physics Letters, vol. 62, no. 7, pp. 714-716, 1993.
[7]V.G. Deibuk, A.V. Biloshytskyi, “Design of a Ternary Reversible/Quantum Adder using Genetic Algorithm”, International Journal of Information Technology and Computer Science (IJITCS), vol. 9, pp. 38-45, 2015.
[8]A. Sajid, A. Nafees, S. Rahman, “Design and Implementation of Low Power 8-bit Carry-look Ahead Adder Using Static CMOS Logic and Adiabatic Logic”, International Journal of Information Technology and Computer Science (IJITCS), vol. 11, pp. 78-92, 2013.
[9]M. Hayati, A. Rezaei, “Design of novel efficient adder and subtractor for quantum-dot cellular automata”, International Journal of Circuit Theory and Applications, vol. 43, no 10, pp.1446-1454, 2015.
[10]H. Bandani Sousan, M. Mosleh, S. Setayeshi, “Designing and Implementing a Fast and Robust Full-Adder in Quantum-Dot Cellular Automata (QCA) Technology”, Journal of Advances in Computer Research, vol. 6, no. 1, pp. 27-45, 2015.
[11]R.R. Devi, S. Thilakavathi, K.M. Suganya, “Clock Zone Based QCA Adder Architecture Design”, International Journal of Advanced Research in Computer Science and Software Engineering, vol. 5 , no. 10, pp. 560-563, 2015.
[12]I. Hänninen, J. Takala. “Binary Adders on Quantum-Dot Cellular Automata,” Journal of Signal Processing Systems, vol. 58, no. 1, pp. 87-103, 2010.
[13]T. Suratkar, “QCA Based Design of Serial Adder,” ITSI-TEEE, vol. 1, no. 5, pp. 57-61, 2013.
[14]K. Walus, G.A. Jullien, V.S. Dimitrov, “Computer arithmetic structures for quantum cellular automata,” Proceedings of the IEEE Conference on Nanotechnology, vol. 2, pp. 1435-1439, 2004.
[15]S. Shin, G. Lee and K. Yoo, “Design of Exclusive-OR Logic Gate on Quantum-Dot Cellular Automata,” International Journal of Control and Automation, vol. 8, no. 2, pp. 95-104, 2015.
[16]K. Walus, G. Schulaf, G.A. Julliaen, “High Level Exploration of Quantum Dot Automata,” Proceedings of the IEEE Conference on Nanotechnology, vol. 1, pp. 30-33, 2004.
[17]K. Walus, W. Wang, G.A. Julliaen, “Quantum Cellular Automata Adders,” Proceedings of the IEEE Conference on Nanotechnology, vol. 2, pp. 461-464, 2003.
[18]I. Amlani, O. Orlov, G. Toth, G.H. Bernstein, C.S. Lent, G.L Snider, “Digital Logic Gate Using Quantum-Dot Cellular Automata,” Science, vol. 284, no. 5412, pp. 289-291, 1999.
[19]H. Cho, E.E. Swartzlander, “Adder designs and analyses for quantum dot cellular automata,” IEEE Trans, Nanotechnol, vol. 6 no. 3, pp. 374-383, 2007.
[20]S. Hashemi, M. Tehrani, K. Navi, “An efficient quantum-dot cellular automata full-adder,” Academic journals, vol. 7, no. 2, pp. 177-189, 2012.
[21]QCADesigner, Available: http://mina.ubc.ca/qcadesigner, 2016.
[22]L. Lim, A.Ghazali, S.C.T. Yan, C.C. Fat, “Sequential circuit design using Quantum-dot Cellular Automata (QCA),” IEEE International Conference on Circuits and Systems (ICCAS), pp. 162-167, 2012.
[23]A. Mostafaee, A. Rezaei, M.M. Karkhanehchi, S.M. Jamshidi, “Design of QCA Full Adders without Wire Crossing,” Boson Journal of Modern Physics, vol. 2, no. 2, pp. 90-96, 2015.
[24]M. Mano, “Digital Design,” California State University, Los Angeles, 2011.
[25]M.R. Beigh, M. Mustafa, F. Ahmad, “Performance Evaluation of Efficient XOR Structures in Quantum-Dot Cellular Automata (QCA),” Scientific Research, vol. 4, no. 2, pp. 147-156, 2013.
[26]M. Hayati and A. Rezaei, “An efficient and optimized multiplexer design for quantum-dot cellular automata,” Journal of Computational and Theoretical Nanoscience, vol. 11, no. 1, pp. 297-302, 2014.
[27]M. H. Moaiyeri, M. Nasiri, N. Khastoo, “An efficient ternary serial adder based on carbon nanotube FETs,” Engineering Science and Technology, vol. 19, no. 1, pp. 271-278, 2016.
[28]S.A. Ebrahimi, P. Keshavarzian, S. Sorouri, M. Shahsavari, “Low power CNTFET-based ternary full adder cell for nanoelectronics,” Int. J. Soft Comput, Eng, vol. 2, no. 2, pp. 291–295, 2012.
[29]P. Keshavarzian, R. Sarikhani, “A novel CNTFET-based ternary full adder,” Circuits Syst Signal Processing, vol. 33, no. 3, pp. 665-679, 2014.