Nowadays, software test is one of the most important activities that software's quality will be certified by it. Test operation includes program's implement on test case set and comparison of results with expected one. Manual test case for operation test program and error detect is time consuming with insufficient precision and complicated coverage of program, so, the use of algorithms in automatic test case generation has been considered. Meta-heuristic algorithms are known tools which are optimized and used in test case generation. Most of complicated matters need a lot of possible states assessment in order to reach the valid answer. With the proper answer, test case optimization and meta-heuristic algorithms play a constructive role. In this paper we would compare methods and their traits, and the software test case generation methods based on meta-heuristic algorithms with their description. 

Biometric identification using vein patterns is a recent technique. The vein patterns are unique to each individual even in twins and they don't change over age except their size. As veins are beneath the skin it is difficult to forge. BOSPHOROUS hand vein database is used in this work. Hand vein images are uploaded first and key points using Scale Invariant Feature Transform (SIFT) are extracted. Then the neural network is used for training these images. Finally neural network is used for testing these images to check whether the image used for testing matches with the existing database or not. Results are computed like False Acceptation Rate (FAR), False Rejection Rate (FRR), accuracy and error per bit stream.

Reversible logic has shown considerable acceptance and growth in the research fields like quantum computing, Nano computing and optical computing promising lower power dissipation. This paper proposes an optimised design single-bit reversible comparator called SKAR gate with a purpose of reducing quantum cost. Besides, this novel SKAR gate is used as a single-bit reversible comparator to construct an optimised design for a four-bit reversible comparator. The paper discusses two designs, one with the use of SKAR gate and other one using a derivative gate constructed from SKAR gate. Since the reversible logic aims at reducing the value of its fundamental parameters viz. quantum cost, garbage outputs, ancillary inputs, delay and number of gates; Both the proposed designs for single-bit and four-bit reversible comparator are compared with other existing designs on the basis of elementary parameters of reversible logic.