International Journal of Computer Network and Information Security(IJCNIS)

ISSN: 2074-9090 (Print), ISSN: 2074-9104 (Online)

Published By: MECS Press

IJCNIS Vol.6, No.4, Mar. 2014

CBC and Interleaved CBC Implementations of PACTS Cryptographic Algorithm

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J. John Raybin Jose, E. George Dharma Prakash Raj

Index Terms

Symmetric Block Cipher;Parallel Cryptography;Adaptive Cryptography;Cipher Block Chaining;Interleaving;Transposition;Substitution


PACTS (Parallelized Adaptive Cipher with Transposition and Substitution) is a new class of Symmetric Cryptographic Algorithm designed using traditional techniques to efficiently utilize the parallel computing capabilities of the modern computing systems. It overcomes the performance inconsistencies prevalent in conventional cryptographic algorithms when they are implemented in different computing systems with different processing capabilities. The size of the key and the plain text blocks of PACTS are each 1024-bits. The adaptive nature of this algorithm is achieved by incorporating flexibility in the size of the key and plain text sub-blocks and the number of rounds. Level of Intra-packet parallelization, variety in grain size and the required security strength are achieved by suitably deciding the sub-block size. Flow of the algorithm is made dynamic by determining the execution steps at runtime using the value of the key. In spite of these advantages PACTS always produces the same cipher text block for a particular plain text block when the same key is used. CBC mode along with 2-way and 4 way Interleaved CBC modes are employed to overcome this problem. The performance of the PACTS in ECB, CBC and Interleaved CBC modes are analyzed with implementations in shared memory parallel computing environment using OpenMP, Java Threads and MPI.

Cite This Paper

J. John Raybin Jose, E. George Dharma Prakash Raj,"CBC and Interleaved CBC Implementations of PACTS Cryptographic Algorithm", IJCNIS, vol.6, no.4, pp.63-71, 2014. DOI: 10.5815/ijcnis.2014.04.08


[1]Jeffrey Hoffstein, Jill Pipher, Joseph H. Silverman, “An Introduction to Mathematical Cryptography”, Springer International Edition, Springer (India) Pvt. Ltd., New Delhi, 2008.

[2]Eric C. Seidel, Joseph N. Gregg, “Preparing Tomorrow’s Cryptography: Parallel Computation via Multiple Processors, Vector Processing, and Multi-Cored Chips”, Research Paper, May 2003.

[3]William Stallings, “Cryptography and Network Security-Principles and Practice”, 5th Edition, Dorling Kindersley (India) Pvt. Ltd., licensees of Pearson Education, 2011.

[4]Menezes A.J., Van Oorschot P.C., Vastone S.A., “Handbook of Applied Cryptography”, CRC Press, 1996.

[5]Schneier B., “Applied Cryptography: Protocols, Algorithms, and Source Code in C”, Second Edition, Wiley & Sons, 1995.

[6]Suman Khakurel, Prabhat Kumar Tiwary, Niwas Maskey, Gitanjali Sachdeva, “Security Vulnerabilities in IEEE 802.11 and Adaptive Encryption Technique for Better Performance”, IEEE Symposium on Industrial Electronics and Applications, Penang, Malaysia, 2010.

[7]Thomas Rauber, Gudula Runger, “Parallel Programming –for Multicore and Cluster Systems”, International Edition, Springer (India) Pvt. Ltd. New Delhi, 2010.

[8]HoWon Kim, YongJe Choi, Kyoil Chung, and HeuiSu Ryu, "Design and Implementation of a Private and Public Key Crypto Processor and Its Application to Security System," proceedings of the 3rd International Workshop on Information Security Applications, pp. 515 – 531, Jeju, Korea, 2002,

[9]Pionteck, T., Staake T., Stiefmeier T., Kabulepa L. D., Glesner M., “Design of reconfigurable AES encryption/decryption engine for mobile terminals”, in the proceedings of the International Symposium on Circuits and Systems, 2004.

[10]Sourav Mukherjee, Bidhudatta Sahoo, “A survey on hardware implementation of IDEA Cryptosystems” Information Security Journal: A Global Perspective, Vol. 20, Nr. 4-5, pp 210-218, 2011.

[11]Tetsuya Ichikawa, Tomomi Kasuya, and Mitsuru. Matsui. “Hardware evaluation of the AES finalists.” In Proc. Third Advanced Encryption Standard Candidate Conference, pages 279–285, USA, 2000.

[12]Bryan Weeks, Mark Bean, Tom Rozylowicz, and Chris Ficke. “Hardware performance simulations of Round 2 Advanced Encryption Standard algorithms”. In Proc. Third Advanced Encryption Standard Candidate Conference, USA, 2000.

[13]Swankoski E. J., Brooks R. R., Narayanan V., Kandemir M., and Irwin M. J., “A Parallel Architecture for Secure FPGA Symmetric Encryption”, proceedings of the 18th International Parallel and Distributed Processing Symposium, Santa Fe, New Mexico, 2004.

[14]Kotturi D., Seong-Moo Y., Blizzard J., “AES crypto chip utilizing high-speed parallel pipelined architecture” proceedings of the IEEE International Symposium on Circuits & Systems, 2005.

[15]Chi-Wu H., Chi-Jeng C., Mao-Yuan L., Hung-Yun T., “The FPGA Implementation of 128-bits AES Algorithm Based on Four 32-bits Parallel Operation”, First International Symposium on Data, Privacy, and E-Commerce, 2007.

[16]Chonglei, M., J. Hai and J. Jennes, “CUDA-based AES Parallelization with fine-tuned GPU memory utilization”, proceedings of the IEEE International Symposium on Parallel and Distributed Processing, Workshops and Ph. D. Forum, pp19-23, 2010.

[17]Julian Ortega, Helmuth Tefeffiz, Christian Treffiz, “Parallelizing AES on Multicores and GPUs”, IEEE International Conference on Electro/Information Technology, Mankato, US, pp. 1-5, 2011.

[18]Li, H. and J. Z. Li, “A new compact dual-core architecture for AES encryption and decryption”, Canadian Journal of Electrical and Computer Engineering, pp 209-213, 2008.

[19]Hua Li., “A parallel S-box architecture for AES byte substitution”, paper presented at IEEE sponsored International Conference on Communication, Circuits and Systems, Chengdu, China, 2004.

[20]Praveen Dongara, T. N. Vijaykumar, Accelerating Private-key cryptography via Multithreading on Symmetric Multiprocessors. In Conference Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, pp 58-69, 2003.

[21]Zadia Codabux-Rossan, M. Razvi Doomum, “AES CCMP Algorithm with N-Way Interleaved Cipher Block Chaining”, University of Mauritius Research Journal, Volume – 15, pp 527-544, 2009.

[22]S. Ashokkumar, K. Karuppasamy, Balaji Srinivasan, V.Balasubramanian “Parallel Key Encryption for CBC and Interleaved CBC” International Journal of Computer Applications, Volume 2–No. 1, 2010.

[23]Bielecki W., Burak D., “Parallelization of Standard Modes of Operation for Symmetric Key Block Ciphers”, Image Analysis, Computer Graphics, Security Systems and Artificial Intelligence Applications Vol 1, Bialystok 2005.

[24]Bielecki W., Burak D., “Parallelization of Symmetric Block Ciphers”, Computing, Multimedia and Intelligent Techniques special issue on Live Biometrics and Security, Vol. 1, Czestochowa University of Technology, June 2005.

[25]J. John Raybin Jose, Dr. E. George Dharma Prakash Raj, “PACTS – A Communication Intensive Symmetric Block Cipher for Parallel Computing Environments” in the proceedings of IEEE International Conference on Research and Development Prospects on Engineering and Technology, Nagapattinam, India, April 2013.