Work place: Electronics and Telecommunication Department of St. Fransis Institute of Technology, Borivali (w), Mumbai, India
E-mail: udaypandit@rediffmail.com
Website:
Research Interests: Wireless Networks, Wireless Communication
Biography
Uday Pandit Khot received his B. E.degree in Industrial Electronics Engineering from the Amravati University, Amravati, M.Tech. in (Electronic Systems, Spec. in Control and Instrumentation), and Ph. D.in Electronic Systems, IIT Bombay,Mumbai, Maharashtra, India. He has been 27 years of Teaching and 10 years of research Experience. He has been Professor of Electronics and Telecommunication,Saint Francis Institute of Technology, Borivali (W), Mumbai, Maharashtra, India since 2012. He received Minor Research Grant from University of Mumbai. He has Professional Memberships of IEEE (USA) Member (Since 2002) Fellow:IETE (India) (Since 2000) Member: IE (India) (Since 2006) Member: ISTE (India) (Since 1994) His research interests include analog and digital circuits, current mode circuits, Wireless Communication, and Mobile Networks.includes the biography here.
By Anand D. Mane Uday Pandit Khot
DOI: https://doi.org/10.5815/ijwmt.2022.02.05, Pub. Date: 8 Apr. 2022
This Research focuses on cross layer approach to enhance the User Experience and Quality Of Service of video streaming in Long Term Evolution mobile network. During run time channel quality index is observed. Application layer requirement is fulfilled by changing modulation techniques as well as dynamic allocation of resources. This paper proposes a algorithm which improves the End-to-End Delay,Peak Signal to Noise Ratio of transmitted video over Mobile Network. Experimental results show the improvement in end to end delay by 89% and Peak Signal to Noise Ratio by 8%. Simulation in Network Simulator-3 provide credible evidence that this proposed cross-layer algorithm outperforms between earlier algorithm in providing better Quality Of Experience for real time, adaptive video streaming over Long Term Evolution.
[...] Read more.By Dipak Marathe Uday Pandit Khot
DOI: https://doi.org/10.5815/ijigsp.2019.11.06, Pub. Date: 8 Nov. 2019
This paper proposes a 10-bit mixed current mode low power SAR ADC for sensor node application. The different entities of a successive approximation register (SAR) analog-to-digital converter (ADC) circuit has a hybrid or mixed mode approach i.e.,voltage mode regenerative comparator; mixed SAR logic; and current mode digital-to-analog converter (DAC). The performance limitation of speed and the kick-back noise of a dynamic comparator is resolved using duty cycle controlled regenerative comparator. A mixed mode logic of a SAR is partitioning the design into synchronous ring counter and asynchronous output register. The data shifting of a ring counter is with the common clock tick while the output register exchanged it asynchronously using handshake signals, resulting in a low power SAR. The current mode switching function in a DAC to reduce asynchronous switching effect resulting in a low energy conversion per step. In overall, the proposed mixed SAR ADC consumes a 41.6 power and achieves an SFDR 69.3 dB at 10 MS/sec and 1 V supply voltage. It is designed and simulated in the 0.18 m TSMC CMOS process.
[...] Read more.Subscribe to receive issue release notifications and newsletters from MECS Press journals