Work place: State Key Lab of Digital Manufacturing Equipment & Technology, Huazhong University of Science and Technology, Wuhan, P.R. China
E-mail: Amo.hust@foxmail.com
Website:
Research Interests: Computer systems and computational processes, Systems Architecture, Distributed Computing, Parallel Computing, Data Structures and Algorithms
Biography
Cheng Xin was was born in P.R. China in 1982 and received his B.S. and M.S. degree in information engineering from Wuhan University of technology, P.R. China in 2004 and 2007 respectively. He is currently a doctoral student in state Key Lab of Digital Manufacturing Equipment & Technology, Huazhong Univ. of Science and Technology (HUST), Wuhan, P.R. China. Cheng Xin’s research interests include networking, parallel and distributed systems, high-speed and high-precise motion control systems. He is now developing the research of precise motion control architecture for 65nm twins-wafer stages Lithography.
DOI: https://doi.org/10.5815/ijeme.2011.05.02, Pub. Date: 29 Nov. 2011
Rapid increases in the complexity of algorithms for real-time signal processing applications have made multi-processors parallel processing technology needed. This paper proposes a design of high-performance real-time bus (RTB), based on which distributed shared memory (DSM) mechanism is established to implement data exchange among multiple processors. Adopting DSM mechanism can reduce the software overhead and improve data processing performance significantly. Definition and implementation details of RTB and data transmission model are discussed. Experimental results show the stable data transmission bandwidth is achieved with performance not affected by the increasing number of processors.
[...] Read more.By Cheng Xin Zhou Yunfei Hu Yongbin Kong Xiangbin
DOI: https://doi.org/10.5815/ijmecs.2010.01.02, Pub. Date: 8 Nov. 2010
Complexity of algorithms for the servo control in the multi-dimensional, ultra-precise stage application has made multi-processor parallel computing technology needed. Considering the specific communication requirements in the parallel servo computing, we propose a communication service scheme based on VME bus, which provides high-performance data transmission and precise synchronization trigger support for the processors involved. Communications service is implemented on both standard VME bus and user-defined Internal Bus (IB), and can be redefined online. This paper introduces parallel servo computing architecture and communication service, describes structure and implementation details of each module in the service, and finally provides data transmission model and analysis. Experimental results show that communication services can provide high-speed data transmission with sub-nanosecond-level error of transmission latency, and synchronous trigger with nanosecond-level synchronization error. Moreover, the performance of communication service is not affected by the increasing number of processors.
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