This paper presents the design and implementation of a new low-cost and minimum embedded board based on TMS320C6713 (PYP 208-PIN (PQFP)) DSP and Spartan-3 (XCS400-4PQG208C) FPGA in two layers with mount elements on two sides of the board. The proposed embedded board was developed satisfactorily for different applications such as data acquisition of sensor’s with serial port, control units, finite state machines, signal processing algorithms, navigation computing, Kalman filtering etc. Goal of the design was to implement as many as possible low-cost and minimum sizes of the board, also to receive input signals in a short time period and as real time. The board features are include: mount elements in two side of the board for minimization of the proposed board and also placed decoupling capacitors (by pass) for the DSP and FPGA in bottom layer of board strictly below these two ICs because should be placed as close as possible to the power supply pins DSP and FPGA, GND polygon layer is used in total top layer and microcomputer ground for DSP & FPGA in bottom layer, use FPGA for two aim ones for implementation of glue logic total of board and interface between serial connectors, use three RS-232 serial port, one RS-422, and SPI serial port on FPGA, use MT48LC16M16A SDRAM-256MB(4*4MB*16), Am29LV400B Flash memory 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) and XCF02S configuration PROM. The size of the proposed embedded board is 11.1cm*17. 7cm so this board is optimized of aspect cost, performance, power, weight, and size.

Microcontrollers and FPGAs both are widely used in digital system design. Microcontroller-based instruments are becoming increasingly widespread. This paper presents design and implementation of a new low-cost and minimum embedded board based on ATMEGA32L AVR microcontroller and Spartan-3 (XCS400-4PQG208C) FPGA in two layers with mount elements on top and button of board. Using of AVR microcontroller in proposed board it adds many features include Analog to Digital Converter (ADC), Digital to Analog Converter (DAC), 32 Kbytes flash memory, 2 Kbytes SRAM, 1024 bytes EEPROM memory. The design goal was to implement as many as possible low-cost and minimum size of the board, also to receive and process input signals in a short time period as real time. The board features are; mount elements in two side of the board for minimization of proposed board and also place decoupling capacitors (by pass) for the FPGA in bottom layer of board strictly below this IC because they should be placed as close as possible to the power supply pins FPGA, use GND polygon layer in total top layer and microcomputer ground for FPGA in bottom layer, use two RS-232 serial port, one VGA connector, PS/2 serial port, and SPI serial port on FPGA, use MT48LC16M16A SDRAM-256MB(4*4MB*16), and XCF02S configuration PROM. Size of the proposed embedded board is 10cm*15cm thus this board was optimized of aspect cost, performance, power, weight, and size.

This paper presents, a high speed FPGA implementation of fully digital controller for three-phase Z-Source Inverter (ZSI) with two switching strategies include simple boost control and maximum boost control. In this method total of blocks are based on proposed digital circuits only with combinational logic and using pipelining technique. Since it is vital to have a high speed and effective ZSI controller, a novel digital design for pulse width modulation control have been implemented for simple and maximum boost control of the ZSI. The proposed digit controllers have been successfully synthesized and implemented by Quartus II 9.1V and Cyclone II FPGA, to target device EP2C20F484C6. Achieved result demonstrates that the proposed method has features including reconfigurable, low-cost, high speed and also it is very accurate.

This paper presents, a low power 128-bit Advanced Encryption Standard (AES) algorithm based on a novel asynchronous self-timed architecture for encryption of audio signals. An asynchronous system is defined as one where the transfers of information between combinatorial blocks without a global clock signal. The self-timed architectures are asynchronous circuits which perform their function based on local synchronization signals called hand shake, independently from the other modules. This new architecture reduced spikes on current consumption and only parts with valid data are working, and also this design does not need any clock pulse. A combinational logic based Rijndael S-Box implementation for the Substitution Byte transformation in AES is proposed, its low area occupancy and high throughput therefore proposed digital design leads to reduction in power consumption. Mix-columns transformation is implemented only based on multiply-by-2 and multiply-by-3 modules with combinational logic. The proposed novel asynchronous self-timed AES algorithm is modeled and verified using FPGA and simulation results from encryption of sound signals is presented, until original characteristics are preserved anymore and have been successfully synthesized and implemented using Xilinx ISE V7.1 and Virtex IV FPGA to target device Xc4vf100. The achieved power consumption is 283 mW in clock frequency of 100 MHz.

This paper focuses on the design of a low power and high performance FPGA based Digital Space Vector Pulse Width Modulation (DSVPWM) controller for three phase voltage source inverter. A new method is proposed to realize easy, accurate and high performance DSVPWM technique based on FPGA with low resource consumption and reduced execution time than conventional methods. Equations of SVPWM are relatively complicated and need a considerable time to execute on a typical microcontroller, therefore a simple method is presented to minimize run time of instructions, e.g. the multiplication operation used in these equations is replaced by a proposed signed and unsigned shifter using 2 to 1 multiplexer unit. Total power consumption of controller is reduced to 37 mW at 100MHz clock frequency. The proposed DSVPWM technique algorithm was synthesized and implemented using Quartus II 9.1V and Cyclone II FPGA, to target device EP2C20F484C6. Also power is analyzed using XPower analyzer. Experimentation and results demonstrate that proposed method have high performance than other works.

In this paper, presents an optimized combinational logic based Rijndael S-Box implementation for the SubByte transformation(S-box) in the Advanced Encryption Standard (AES) algorithm on FPGA. S-box dominated the hardware complexity of the AES cryptographic module thus we implement its mathematic equations based on optimized and combinational logic circuits until dynamic power consumption reduced. The complete data path of the S-box algorithm is simulated as a net list of AND, OR, NOT and XOR logic gates, also for increase in speed and maximum operation frequency used 4-stage pipeline in proposed method. The proposed implemented combinational logic based S-box have been successfully synthesized and implemented using Xilinx ISE V7.1 and Virtex IV FPGA to target device Xc4vf100. Power is analized using Xilinx XPower analyzer and achieved power consumption is 29 mW in clock frequency of 100 MHz. The results from the Place and Route report indicate that maximum clock frequency is 209.617 MHz.

This paper presents, complete step by step description design and implementation of a high speed technique for character segmentation of license plate based on thresholding algorithm. Because of vertical edges in the plate, fast Sobel edge detection has been used for extracting location of license plate, after stage edge detection the image is segmented by thresholding algorithm and the color of characters is changed to white and the color of background is black. Then, boundary’s pixels of license plate are scanned and their color is changed to black pixels. Afterward the image is scanned vertically and if the number of black pixels in a column is equal to the width of plate or a little few, then the pixels of that column is changed to white pixel, until create white columns between characters, in continue we change pixels around license plate to white pixels. Finally characters are segmented cleanly. We test proposed character segmentation algorithm for stage recognition of number by code that we design. Results of experimentation on different images demonstrate ability of proposed algorithm. The accuracy of proposed character segmentation is 99% and average time of character segmentation is 15ms with thresholding algorithm code and 0.7ms only segmentation character code that is very small in comparison with other algorithms.