Multimedia communications in wireless sensor networks is a very challenging task. Video coding with high computational complexity and great contribution to the energy consumption of nodes and video transmission over erroneous wireless channel are the main reasons of these challenges. Distributed Video Coding has high potential for being deployed in these networks due to its unique features like as independent frame coding and low complexity encoding operations. The purpose of this study is to understand and evaluate the distributed video coding performance facing the transmission characteristics in wireless multimedia sensor networks. To this end, the comparative analysis of the coding in respect of main factors of video transmission (i.e., bit rate and error resiliency) in the Wireless Multimedia Sensor Networks (WMSN) has been done. We have used both the objective and subjective criteria for checking the video quality and applied the Gilbert-Elliot channel model for capturing the bit-level error in WMSN. Therefore, unlike previous works, our results are more realistic. In addition, based on this model we have investigated the impact of protection of frames by Reed-Solomon error control scheme. The results show that paying attention to coding parameters and protecting key frames, have a great impact on increasing the quality of the receiving video and will reduce the energy consumption and delays due to low number of requests from the feedback channel.

Face detection and recognition has always been one of the research interests to researchers in the field of the biometric identification of individuals. Problems such as environmental lighting, different skin color, complex background, etc affect on the detection and recognition of individuals. This paper proposes a method to enhance the performance of face detection and recognition systems. Our method, basically consists of two main parts: firstly, we detect faces and then recognize the detected faces. In the detection step, we use the skin color segmentation combined with AdaBoost algorithm, which is fast and also more accurate compared to the other known methods. Also, we use a series of morphological operators to improve the face detection performance. Recognition part consists of three steps: dimension reduction using Principal Component Analysis (PCA), feature selection using Linear Discriminant Analysis (LDA), and k-Nearest Neighbor (K-NN) or Support Vector Machine (SVM) based classification. Combination of PCA and LDA is used for improving the capability of LDA when a few samples of images are available. We test the system on the face databases. Experimental results show that the system is robust enough to detect faces in different lighting conditions, scales, poses, and skin colors from various races. Also, the system is able to recognize face with less misclassification compared to the previous methods.

Capturing is the first step in intrusion detection system (IDS). Having wire speed, omitting the OS from capturing process and no need for making a copy of packets from the system’s environment to the user’s environment are some of the system characteristics. If these requirements are not met, packet capture system is considered as the main bottleneck of IDS and the overall efficiency of this system will be influenced. Presence of all these three characteristics calls for utilization of hardware methods. In this paper, by using of FPGA, a line sniffing and load balancing system are designed in order to be applied in IDS systems. The main contribution of our work is the feasibility of attaching labels to the beginning part of each packet, aiming at quick easy access of other IDS modules to information of each packet and also reducing workload of these modules. Packet classification in the proposed system can be configured to 2, 3, and 5 tuple, which can also be applied in IDS detection module in addition to load balancing part of this system. Load balancing module uses Hash table and its Hash function has the least flows collisions. This system is implemented on a set of virtex 6 and 7 families and is able to capture packets 100% and perform the above mentioned processes by speed of 12 Gbit/s.