Increase in the population of India, results in higher demand for food as well as decrease in land for farming. Hence to fulfil the increased demand, food is adulterated to get more quantity in short period of time. Moreover, pesticides in crops are using above the legal maximum residue limit by farmers to gain more profit in lesser time. Although pesticides are highly effective on pests but they can reside in an environment. Among the class of organophosphate pesticides, chlorpyrifos is widely used in vegetables. Chlorpyrifos has toxic effects on the human body particularly on brain and nervous system. In this paper, design and development of sensors for pesticide residue detection using parameters like electrical conductivity, pH etc are proposed. It was found that the relative percentage deviation between the value of conductivity in pesticide free samples and the pesticide containing samples of bitter gourd, bottle gourd and tomatoes are 31.4%, 10.7% and 19.09% and also between pesticide free samples and market samples are 33.5%, 8.7% and 16.56% respectively. This large variation among different samples shows the presence of pesticide residue. Hence, the method can be successfully used for the detection of pesticide residues in vegetable samples. The proposed sensor system is easy, rapid and time undemanding method. So, this electronic device can also be used to check impurities in any other liquid like water, milk etc.

The complexity of the system design is increasing very rapidly as the number of transistors on Integrated Circuits (IC) doubles as per Moore’s law. There is big challenge of testing this complex VLSI circuit, in which whole system is integrated into a single chip called System on Chip (SOC). Cost of testing the SOC is also increasing with complexity. Cost modeling plays a vital role in reduction of test cost and time to market. This paper includes the cost modeling of the SOC Module testing which contains both analog and digital modules. The various test cost parameters and equations are considered from the previous work. The mathematical relations are developed for cost modeling to test the SOC further cost modeling equations are modeled in Graphical User Interface (GUI) in MATLAB, which can be used as a cost estimation tool. A case study is done to calculate the cost of the SOC testing due to Logic Built in Self Test (LBIST) and Memory Built in Self Test (MBIST). VLSI Test engineers can take the benefits of such cost estimation tools for test planning.