Bezier curve is one of the most pragmatic curves that has vast application in computer aided geometry design. Unlike other normal curves, any Bezier curve model must follow the properties of Bezier curve. In our paper, we proposed the reconstruction of Bezier models by implementing satisfiability problem in Hopfield neural network as Bezier properties verification technique. We represent our logic construction to 2-satisfiability (2SAT) clauses in order to represent the properties of the Bezier curve model. The developed Bezier model will be integrated with Hopfield neural network in order to detect the existence of any non-Bezier curve. Microsoft Visual C++ 2013 is used as a platform for training, testing and validating of our proposed design. Hence, the performance of our proposed technique is evaluated based on global Bezier model and computation time. It has been observed that most of the model produced by HNN-2SAT are Bezier curve models.

Highly-interconnected Hopfield network with Content Addressable Memory (CAM) are shown to be extremely effective in constraint optimization problem. The emergent of the Hopfield network has producing a prolific amount of research. Recently, 3 Satisfiability (3-SAT) has becoming a tool to represent a variety combinatorial problems. Incorporated with 3-SAT, Hopfield neural network (HNN-3SAT) can be used to optimize pattern satisfiability (Pattern-SAT) problem. Hence, we proposed the HNN-3SAT with Hyperbolic Tangent activation function and the conventional McCulloch-Pitts function. The aim of this study is to investigate the accuracy of the pattern generated by our proposed algorithms. Microsoft Visual C++ 2013 is used as a platform for training, testing and validating our Pattern-SAT design. The detailed performance of HNN-3SAT of our proposed algorithms in doing Pattern-SAT will be discussed based on global pattern-SAT and running time. The result obtained from the simulation demonstrate the effectiveness of HNN-3SAT in doing Pattern-SAT.

Very large scale integration (VLSI) circuit comprises of integrated circuit (IC) with transistors in a single chip, widely used in many sophisticated electronic devices. In our paper, we proposed VLSI circuit design by implementing satisfiability problem in Hopfield neural network as circuit verification technique. We restrict our logic construction to 2-Satisfiability (2-SAT) and 3-Satisfiability (3-SAT) clauses in order to suit with the transistor configuration in VLSI circuit. In addition, we developed VLSI circuit based on Hopfield neural network in order to detect any possible error earlier than the manual circuit design. Microsoft Visual C++ 2013 is used as a platform for training, testing and validating of our proposed design. Hence, the performance of our proposed technique evaluated based on global VLSI configuration, circuit accuracy and the runtime. It has been observed that the VLSI circuits (HNN-2SAT and HNN-3SAT circuit) developed by proposed design are better than the conventional circuit due to the early error detection in our circuit.