In bandpass modulators, a 2N-order loop filter can lead to an N-order noise shaping in the band of interest. This caused a bandpass modulator with more complex structure than a lowpass modulator and increased the power consumption and area of the modulator. In this paper, we proposed a discrete-time bandpass modulator using the noise-coupling technique that only needs to a second- order loop filter to have a second-order noise shaping. To realize a noise coupled bandpass modulator, we need to implement Z-2 delay block in the analog domain, but the proposed modulator uses only Z-1 delay blocks to apply the noise coupling technique. This simplifies the structure of the modulator and reduces the power consumption, area, and nonlinearity of the modulator. The error in the coupling path is considered and the effect of it on the modulator resolution is analyzed. According to the simulation results, the proposed modulator results in SNR = 84.9 dB at 80 MHz sampling frequency, 200 KHz bandwidth and OSR = 200.

Jitter is one of the most important parameters in design of delay locked loop (DLL) based frequency synthesizer. In this paper noise and mismatches of conventional delay cells which are mainly used in the DLLs architecture are introduced completely. First, time domain equations related to noise and mismatches of conventional delay cells are reported. Then, these equations are used to calculate jitter of DLL due to mismatch and noise of delay cells. At last closed form equations are obtained which can be used in the designing of low jitter DLLs. To validate these equations, a conventional DLL is designed in TSMC 0.18um CMOS Technology.