Work place: NXP Semiconductors Noida, India
E-mail: ravi.teja.4.1994@gmail.com
Website:
Research Interests: Data Structures, Data Compression, Computer Networks, Neural Networks, Artificial Intelligence
Biography
Ravi Teja Yakkali was born in Andhra Pradesh, India. Currently, he is Design Engineer-I at NXP Semiconductors, Noida working on Automotive Integrated Circuits Validation researching in Automotive Radars which involves research in the domains of Embedded Systems, Digital Signal Processing, Data Processing and Machine Learning. He is a research enthusiast especially in the field of Embedded Systems, Digital Signal Processing, Automotive Radars, Artificial Intelligence, Wireless Sensor Networks, Neural Networks, Data Processing, Machine Learning, Antenna Design, Analog Filters. He completed this research work while pursuing his 4th year at Delhi Technological University, Delhi.
By Ravi Teja Yakkali N S Raghava
DOI: https://doi.org/10.5815/ijigsp.2017.10.05, Pub. Date: 8 Oct. 2017
Information processing using Neural Network Counter can result in faster and accurate computation of data due to their parallel processing, learning and adaptability to various environments. In this paper, a novel 4-Bit Negative Edge Triggered Binary Synchronous Up/Down Counter using Artificial Neural Networks trained with hybrid algorithms is proposed. The Counter was built solely using logic gates and flip flops, and then they are trained using different evolutionary algorithms, with a multi objective fitness function using the back propagation learning. Thus, the device is less prone to error with a very fast convergence rate. The simulation results of proposed hybrid algorithms are compared in terms of network weights, bit-value, percentage error and variance with respect to theoretical outputs which show that the proposed counter has values close to the theoretical outputs.
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