Work place: Integral University, Lucknow, India
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Research Interests: Computer Networks, Network Architecture, Network Security
Biography
Mr. Ahmad Nafees received M.S. degree in Communication Engineering from York University, U.K. in 2011 and B.Tech degree in Electronics & Communication Engineering from Integral University in 2009. Currently, he is Assistant Professor, Department of E&C Engineering, Integral University, Lucknow, India. His research interest includes wireless communication.
By Abdul Sajid Ahmad Nafees Saifur Rahman
DOI: https://doi.org/10.5815/ijitcs.2013.11.09, Pub. Date: 8 Oct. 2013
Addition forms the basic structure for many processing operations like counting, multiplication, filtering etc. Adder circuits that add two binary numbers are of great interest for many designers. The simplest approach to design an adder is to implement gates to yield the required logic function. Carry-look ahead adder is a major functional block in arithmetic logic unit due to its high speed operation. The arithmetic logic unit has been widely used in microprocessor systems and mostly in processing modules of embedded systems. Therefore, it is of interest to study the functional behavior and power consumption carry-look ahead adder. In this project, the adder is implemented using 180 nm CMOS technology on bulk substrate. Two logic families i.e. static CMOS and adiabatic logic have been analyzed and implemented to study the transient characteristics of the adder. Finally the power consumption is estimated and compared. From the results it has been found that the static CMOS logic offers low delay whereas the adiabatic logic consumes low power.
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