International Journal of Computer Network and Information Security (IJCNIS)
IJCNIS Vol. 17, No. 2, 8 Apr. 2025
Cover page and Table of Contents: PDF (size: 1633KB)
∆DHT-Zip: A Delta-difference Hybrid Tree Coding Scheme for End-to-end Packet Compression Framework in Network-on-Chips
PDF (1633KB), PP.19-33
Views: 0 Downloads: 0
Author(s)
Index Terms
NoC Framework, Data Packet De/compression, Delta Difference, Time Series Approach, Huffman Tree Encoding, DNA Tree
Abstract
Due to the maximal transistor count, Multi-Processor System-on-Chip (MPSoC) delivers more performance than uniprocessor systems. Network on Chip (NoC) in MPSoC provides scalable connectivity compared to traditional bus-based interconnects. Still, NoC designs significantly impact MPSoC design as it increases power consumption and network latency. A solution to this problem is packet compression which minimizes the data redundancy within NoC packets and reduces the overall power consumption of the whole network by minimizing a data packet size. Latency and overhead of compressor and decompressor require more memory access time, even though the packet compression is good for the improved performance of NoC. So, this problem demands a simple and lightweight compression method like delta compression. Consequently, this research proposes a new delta-difference Hybrid Tree coding (∆DHT-Zip) to de/compress the data packet in the NoC framework. In this compression approach, the Delta encoding, Huffman encoding and DNA tree (deoxyribonucleic acid) coding are hybridized to perform the data packet de/compression approach. Moreover, a time series approach named Run Length Encoding (RLE) is used to compress the metadata obtained from both the encoding and decoding processes. This research produces decreased packet loss and significant power savings by using the proposed ∆DHT-Zip method. The simulation results show that the proposed ∆DHT-Zip algorithm minimizes packet latency and outperforms existing data compression approaches with a mean Compression Ratio (CR) of 1.2%, which is 79.06% greater than the existing Flitzip algorithm.
Cite This Paper
T. Pullaiah, K. Manjunathachari, B. L. Malleswari, "∆DHT-Zip: A Delta-difference Hybrid Tree Coding Scheme for End-to-end Packet Compression Framework in Network-on-Chips", International Journal of Computer Network and Information Security(IJCNIS), Vol.17, No.2, pp.19-33, 2025. DOI:10.5815/ijcnis.2025.02.02
Reference
[1]Shim, Jae Eun, Mingu Kang, and Tae Hee Han. “NCDE: In-Network Caching for Directory Entries to Expedite Data Access in Tiled-Chip Multiprocessors”. IEEE Access. 11 (2023): 3080-95.
[2]Arcas Abella, Oriol. "Multicore architecture prototyping on reconfigurable devices." (2016).
[3]Ilic, Aleksandar, Frederico Pratas, and Leonel Sousa. "Beyond the roofline: Cache-aware power and energy-efficiency modeling for multi-cores." IEEE Transactions on Computers 66, no. 1 (2016): 52-58.
[4]Zhan, Jia. "The Interconnect of Things for Energy-Efficient Multicore Architectures." PhD diss., University of California, Santa Barbara, 2016.
[5]Alazemi, Fawaz, Arash Azizimazreah, Bella Bose, and Lizhong Chen. "Routerless network-on-chip." In 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 492-503. IEEE, 2018.
[6]Oveis-Gharan, Masoud, and Gul N. Khan. "Reconfigurable on-chip interconnection networks for high performance embedded SoC design." Journal of Systems Architecture 106 (2020): 101711.
[7]Wang, Ke, Ahmed Louri, Avinash Karanth, and Razvan Bunescu. "IntelliNoC: A holistic design framework for energy-efficient and reliable on-chip communication for manycores." In Proceedings of the 46th International Symposium on Computer Architecture, pp. 589-600. 2019.
[8]Alimi, Isiaka A., Romil K. Patel, Oluyomi Aboderin, Abdelgader M. Abdalla, Ramoni A. Gbadamosi, Nelson J. Muga, Armando N. Pinto, and António L. Teixeira. "Network-on-chip topologies: Potentials, technical challenges, recent advances and research direction." Network-on-Chip-Architecture, Optimization, and Design Explorations (2021).
[9]Guo, Lei, Weigang Hou, and Pengxing Guo. "Designs of 3D mesh and torus optical Network-on-Chips: Topology, optical router and routing module." China Communications 14, no. 5 (2017): 17-29.
[10]Jerger, Natalie D. Enright, Tushar Krishna, Li-Shiuan Peh, and Margaret Martonosi. On-chip networks. Vol. 12, no. 3. Morgan & Claypool, 2017.
[11]Farrokhbakht, Hossein, Mohammadkazem Taram, Behnam Khaleghi, and Shaahin Hessabi. "Toot: an efficient and scalable power-gating method for noc routers." In 2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), pp. 1-8. IEEE, 2016.
[12]Reddy, B. Naresh Kumar, and Aruru Sai Kumar. “Evaluating the Effectiveness of Bat Optimization in an Adaptive and Energy-Efficient Network-on-Chip Routing Framework”. Journal of Parallel and Distributed Computing. (2024): 104853.
[13]Ali, Haider, Umair Ullah Tariq, James Hardy, Xiaojun Zhai, Liu Lu, Yongjun Zheng, Faycal Bensaali, Abbes Amira, Kaniz Fatema, and Nikos Antonopoulos. "A survey on system level energy optimisation for MPSoCs in IoT and consumer electronics." Computer Science Review 41 (2021): 100416.
[14]Evaldsson, Mattias. "NoC for Versatile Micro-Code Programmable Multi-Core Processor Targeting Convolutional Neural Networks." (2021).
[15]Deepu, Chacko John, Chun-Huat Heng, and Yong Lian. "A hybrid data compression scheme for power reduction in wireless sensors for IoT." IEEE transactions on biomedical circuits and systems 11, no. 2 (2016): 245-254.
[16]Chen, Yuechen, and Ahmed Louri. “An approximate communication framework for network-on-chips”. IEEE Transactions on Parallel and Distributed Systems. 31, no. 6 (2020): 1434-46.
[17]Vafaiee, M., Majid Jalili, Reza Sabbaghi-Nadooshan, and Hamid Sarbazi-Azad. "An efficient on-chip network with packet compression capability." In 2016 International SoC Design Conference (ISOCC), pp. 7-8. IEEE, 2016.
[18]Sardashti, Somayeh, Angelos Arelakis, Per Stenström, and David A. Wood. A primer on compression in the memory hierarchy. Morgan & Claypool, 2016.
[19]Orosa, Lois, and Rodolfo Azevedo. "Temporal frequent value locality." In 2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 147-152. IEEE, 2016.
[20]Lee, Sangpil, Keunsoo Kim, Gunjae Koo, Hyeran Jeon, Won Woo Ro, and Murali Annavaram. "Warped-compression: Enabling power efficient GPUs through register compression." ACM SIGARCH Computer Architecture News 43, no. 3S (2015): 502-514.
[21]Tsai, Po-An, and Daniel Sanchez. "Compress objects, not cache lines: An object-based compressed memory hierarchy." In Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 229-242. 2019.
[22]Wang, Ying, Yinhe Han, Jun Zhou, Huawei Li, and Xiaowei Li. "DISCO: A low overhead in-network data compressor for energy-efficient chip multi-processors." In Proceedings of the 53rd Annual Design Automation Conference, pp. 1-6. 2016.
[23]Ilkhechi, Amir, Andrew Crotty, Alex Galakatos, Yicong Mao, Grace Fan, Xiran Shi, and Ugur Cetintemel. "DeepSqueeze: deep semantic compression for tabular data." In Proceedings of the 2020 ACM SIGMOD international conference on management of data, pp. 1733-1746. 2020.
[24]Vivekananda G, Thejaswini P. “Extended Base-Delta Compression Technique for On-chip Data Transfer”. In2021 IEEE 18th India Council International Conference (INDICON) (2021): 1-7).
[25]Vivekananda, G., and P. Thejaswini. "Extended Base-Delta Compression Technique for On-chip Data Transfer." In 2021 IEEE 18th India Council International Conference (INDICON), pp. 1-7. IEEE, 2021.
[26]Boyapati, Rahul, Jiayi Huang, Pritam Majumder, Ki Hwan Yum, and Eun Jung Kim. "APPROX-NoC: A data approximation framework for network-on-chip architectures." In Proceedings of the 44th Annual International Symposium on Computer Architecture, pp. 666-677. 2017.
[27]Chen, Yuechen, and Ahmed Louri. "An approximate communication framework for network-on-chips." IEEE Transactions on Parallel and Distributed Systems 31, no. 6 (2020): 1434-1446.
[28]Reza, Md Farhadur, and Paul Ampadu. "Approximate communication strategies for energy-efficient and high performance NoC: Opportunities and challenges." In Proceedings of the 2019 on Great Lakes Symposium on VLSI, pp. 399-404. 2019.
[29]Li, Xingyu, and Tushar Sondhi. "FlitReduce: Improving Memory Fabric Performance via End-to-End Network Packet Compression."
[30]Deb, Dipika, M. K. Rohith, and John Jose. "Flitzip: Effective packet compression for noc in multiprocessor system-on-chip." IEEE Transactions on Parallel and Distributed Systems 33, no. 1 (2021): 117-128.
[31]Niwa, Naoya, Yoshiya Shikama, Hideharu Amano, and Michihiro Koibuchi. "A case for low-latency network-on-chip using compression routers." In 2021 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), pp. 134-142. IEEE, 2021.
[32]Deb, Dipika, M. K. Rohith, and John Jose. "Flitzip: Effective packet compression for noc in multiprocessor system-on-chip." IEEE Transactions on Parallel and Distributed Systems 33, no. 1 (2021): 117-128.
[33]Ahmad, Khurshid, Muhammad Athar Javed Sethi, Rehmat Ullah, Imran Ahmed, Amjad Ullah, Naveed Jan, and Ghulam Mohammad Karami. "Congestion-aware routing algorithm for NoC using data packets." Wireless Communications and Mobile Computing 2021 (2021): 1-11.
[34]Saidani, Abdeldjalil, Xiang Jianwen, and Deloula Mansouri. "A lossless compression approach based on delta encoding and T-RLE in WSNs." Wireless Communications and Mobile Computing 2020 (2020): 1-10.
[35]Mishra, Pooja, Chiranjeev Bhaya, Arup Kumar Pal, and Abhay Kumar Singh. "Compressed DNA coding using minimum variance Huffman tree." IEEE Communications Letters 24, no. 8 (2020): 1602-1606.
[36]Pullaiah, T., K. Manjunathachari, and B. L. Malleswari. "BΔ-NIS: Performance analysis of an efficient data compression technique for on-chip communication network." Integration 89 (2023): 83-93.
[37]Zhan, Jia, Matt Poremba, Yi Xu, and Yuan Xie. "NoΔ: Leveraging delta compression for end-to-end memory access in NoC based multicores." In 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), IEEE, (2014): 586-591.