International Journal of Computer Network and Information Security (IJCNIS)
IJCNIS Vol. 4, No. 2, 8 Mar. 2012
Cover page and Table of Contents: PDF (size: 278KB)
Hardware Implementation of Elliptic Curve Cryptography over Binary Field
Full Text (PDF, 278KB), PP.1-7
Views: 0 Downloads: 0
Author(s)
Sandeep S.V
1,*
Hameem Shanavas .I
1
Nallusamy.V
1
Brindha.M
1
Index Terms
Scalar Multiplication, MontgomeryModular Multiplication, Binary field, ECC
Abstract
This paper presents high-performance Elliptic Curve Cryptography (ECC) architecture over binary field, based on the Montgomery scalar multiplication algorithm. The word-serial finite field arithmetic unit (AU) is proposed with the optimized operation scheduling and bit-parallel modular reduction. With a dedicated squarer, the 163-bit point scalar multiplication with coordinate conversion can be done in 20.9μs by the design of one AU, and can be further improved to 11.1μs by the one of three AUs, both using 0.13μm CMOS technology. The comparison with other ECC designs justifies the effectiveness of the proposed architecture in terms of performance and area-time efficiency.
Cite This Paper
Sandeep S.V, Hameem Shanavas.I, Nallusamy.V, Brindha.M, "Hardware Implementation of Elliptic Curve Cryptography over Binary Field", International Journal of Computer Network and Information Security(IJCNIS), vol.4, no.2, pp.1-7, 2012. DOI:10.5815/ijcnis.2012.02.01
Reference
[1]Certicom Corporation, The Basics of ECC 2006[Online] available: http://www.certicom.com/indexphp? Action=res, ecc_fa
[2]IEEE 1363 standard specifications for public-key cryptography, 1363, Jan. 2000
[3]B. Ansari and M. A. Hasan, “High-performance architecture of elliptic curve scalar multiplication” IEEE Trans. Computers, vol. 57, no. 11,pp. 1143–1153, Nov. 2008.
[4]K. Jarvinen and J. Skytta, “On parallelization of high-speed processors for elliptic curve cryptography” IEEE Trans. Very Large Scale Integer. (VLSI) Syst., vol. 16, no. 9, pp. 1162–1175, Sep. 2008.
[5]Z.-B. Dai, F. Qin, and X.-H. Yang, “Scalable hardware architecture for Montgomery inversion computation in dual-field” in Proc. WASE Int.Conf. Inf. Eng., Taiyuan, China, Jul. 2009, pp. 206–209.
[6]Yaxun Gong, Shuguo Li,”High-Throughput FPGA Implementation of 256-bit Montgomery Modular Multiplier” in Proc IEEE on Second International Workshop on Education Technology and Computer Science, (ETCS), Jan 2010,pp.173-177.
[7]G. Chen, G. Bai, and H. Chen, “A dual-field elliptic curve cryptographic processor based on a systolic arithmetic unit” in Proc. IEEE Int. Symp.Circuits Syst. (ISCAS), Seattle, WA, May 2008, pp. 3298–3301.
[8]J.-Y. Lai and C.-T. Huang, “Elixir: High-throughput cost-effective dualfieldProcessors and the design framework for elliptic curve cryptography” IEEE Trans. Very Large Scale Integer. (VLSI) Syst., vol. 16, no. 11, pp. 1567–1580, Nov. 2008.
[9]J.-Y. Lai and C.-T. Huang, “A highly efficient cipher processor for dual field elliptic curve cryptography” IEEE Trans. Circuits Syst. II, Expr. Briefs, vol. 56, no. 5, pp. 394–398, May 2009.
[10]J. Lopez and R. Dahab, “Improved algorithms for elliptic curve arithmetic in GF (2m)” in Proc. Sel. Areas Cryptography: 5th Annu. Int. Workshop (SAC), Aug. 1998, vol. 1556, pp. 201–212.
[11]C.J.McIvor, M.McLoone, and J.V.McCanny,”Hardware Elliptic Curve Cryptographic Processor over GF (P)” IEEE Transacitons on circuits and systems-I: Regular Papers. VOL.53.No.9, September 2006
[12]B. S. Kaliski Jr., “The Montgomery inverse and its applications” IEEE Trans. Computers, vol. 44, no. 8, pp. 1064–1065, Aug. 1995.
[13]E. Savas，, M. Naseer, A. A. A. Gutub, and C. K. Koc, “Efficient unified Montgomery inversion with multibit shifting” IEEE Proc. — Comput.Digit. Techn. vol. 152, no. 4, pp. 489–498, Jul. 2005.
[14]J.-Y. Lai and C.-T. Huang, “Energy-Adaptive Dual-Field Processor for High-Performance Elliptic Curve Cryptographic Applications” IEEE Trans. Onvery large scale integration (VLSI) systems.vol 56, no. 4, pp.356-360, March 2010.
[15]J. Goodman and A. P. Chandrakasan, “An energy-efficient reconfigurable public-key cryptography processor” IEEE J. Solid-StateCircuits, vol. 36, no. 11, pp. 1808–1820, Nov. 2001.