International Journal of Computer Network and Information Security (IJCNIS)
IJCNIS Vol. 7, No. 12, 8 Nov. 2015
Cover page and Table of Contents: PDF (size: 688KB)
FPGA Implementation of Secure Force (64-Bit) Low Complexity Encryption Algorithm
Full Text (PDF, 688KB), PP.60-69
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Author(s)
Shujaat Khan
1,*
M. Sohail Ibrahim
1
Mansoor Ebrahim
2
Haseeb Amjad
1
Index Terms
SF (Secure Force), FPGA, ASIC, WSN (Wireless Sensor Networks), security algorithms, Hardware implementation
Abstract
Field-Programmable Gate Arrays (FPGAs) have turned out to be a well-liked target for implementing cryptographic block ciphers, a well-designed FPGA solution can combine some of the algorithmic flexibility and cost efficiency of an equivalent software implementation with throughputs that are comparable to custom ASIC designs. The recently proposed Secure Force (SF) shows good results in terms of resource utilization compared to older ciphers. SF appears as a promising choice for power and resource constrained secure systems and is well suited to an FPGA implementation. In this paper we explore the design decisions that lead to area/delay tradeoffs in a full loop-unroll implementation of SF-64 on FPGA. This work provides hardware characteristics of SF along with implementation results that are optimal in terms of throughput, latency, power utilization and area efficiency.
Cite This Paper
Shujaat Khan, M. Sohail Ibrahim, Mansoor Ebrahim, Haseeb Amjad, "FPGA Implementation of Secure Force (64-Bit) Low Complexity Encryption Algorithm", International Journal of Computer Network and Information Security(IJCNIS), vol.7, no.12, pp.60-69, 2015. DOI:10.5815/ijcnis.2015.12.07
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