International Journal of Computer Network and Information Security (IJCNIS)
IJCNIS Vol. 9, No. 11, 8 Nov. 2017
Cover page and Table of Contents: PDF (size: 623KB)
Interconnect Network on Chip Topology in Multi-core Processors: A Comparative Study
Full Text (PDF, 623KB), PP.52-62
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Author(s)
Manju Khari
1
Raghvendra Kumar
2
Dac-Nhuong Le
3,*
Jyotir Moy Chatterjee
4
Index Terms
Topology, Multicore Processor, Multi2sim Simulator, Super Scalar, Pipeline
Abstract
A variety of technologies in recent years have been developed in designing on-chip networks with the multicore system. In this endeavor, network interfaces mainly differ in the way a network physically connects to a multicore system along with the data path. Semantic substances of communication for a multicore system are transmitted as data packets. Thus, whenever a communication is made from a network, it is first segmented into sub-packets and then into fixed-length bits for flow control digits. To measure required space, energy & latency overheads for the implementation of various interconnection topologies we will be using multi2sim simulator tool that will act as research bed to experiment various tradeoffs between performance and power, and between performance and area requires analysis for further possible optimizations.
Cite This Paper
Manju Khari, Raghvendra Kumar, Dac-Nhuong Le, Jyotir Moy Chatterjee, "Interconnect Network on Chip Topology in Multi-core Processors: A Comparative Study", International Journal of Computer Network and Information Security(IJCNIS), Vol.9, No.11, pp.52-62, 2017. DOI:10.5815/ijcnis.2017.11.06
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