International Journal of Engineering and Manufacturing (IJEM)
IJEM Vol. 3, No. 2, 16 Sep. 2013
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Design Of A Optimized Parallel Array Multiplier Using Parallel Prefix Adder
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Author(s)
Index Terms
Array multiplier, carry save adder (CSA), Kogge stone Adder, parallel prefix adder ripple carry adder, Microwind, DSCH.
Abstract
Multiplication is the basic building block for several DSP processors, Image processing and many other. Over the years the computational complexities of algorithms used in Digital Signal Processors (DSPs) have gradually increased. This requires a parallel array multiplier to achieve high execution speed or to meet the performance demands. A typical implementation of such an array multiplier is Braun design. Braun multiplier is a type of parallel array multiplier. The architecture of Braun multiplier mainly consists of some Carry Save Adders, array of AND gates and one Ripple Carry Adder. In this research work, a new design of Braun Multiplier is proposed and this proposed design of multiplier uses a very fast parallel prefix adder (Brent kung Adder) in place of Ripple Carry Adder. The architecture of standard Braun Multiplier is modified in this work for reducing the area and delay due to Ripple Carry Adder and performing faster multiplication of two binary numbers. The design is implemented using Microwind1, digital schematics (DSCH)
Cite This Paper
K.KalaiKaviya,D.P.Balasubramanian,S.Tamilselvan,"Design Of A Optimized Parallel Array Multiplier Using Parallel Prefix Adder", IJEM, vol.3, no.2, pp.40-50, 2013. DOI: 10.5815/ijem.2013.02.03
Reference
[1]Muhammad H. Rais, “Hardware Implementation of Truncated Multipliers Using Spartan-3AN, Virtex-4 and Virtex-5 FPGA Devices”, Am. J. Engg. & Applied Sci., 3 (1): 201-206, 2010.
[2]Skalansky “conditional sum additions logic” IRE Transactions, Electronic Computers, vol, EC – 9, pp, 226 - 231, June 1960.
[3]Kogge P, Stone H, “A parallel algorithm for the efficient solution of a general class Recurrence relations”, IEEE Trans. Computers, vol.C-22, No.8, pp 786-793, Aug.1973.
[4]Brent R, Kung H, “A regular layout for parallel adders”. IEEE Trans, computers, Vol.C-31, no.3, pp 260-264, March1982 Academy of Science, Engineering and Technology.
[5]R ,Anitha, and V, Bagyaveereswaran (September 2011). “Braun’s Multiplier Implementation using FPGA with Bypassing Techniques”, International Journal of VLSI design & Communication Systems (VLSICS), Vol.2, No.3.
[6]Seng, Yeo Kiat and Roy, Kaushik (2009). “Low Voltage, Low Power VLSI Subsystems”, TMC.
[7]Wanhannar, Lars (May 2008). “DSP Integrated Circuits”, Academic Press.
[8]Weste, Neil, Harris, David and Banerjee, Ayan (2009). “CMOS VLSI Design: A circuits and system perspective”, Pearson education.
[9]Wen, M.-C., Wang, S.-J. and Lin Y.-N.(12th May 2005). “Low-power parallel multiplier with column bypassing” ELECTRONICS LETTERS, Vol. 41 No. 10.
[10]P.Ramanathan and.P.T.Vanathi, “Hybrid Prefix Adder Architecture for Minimizing the Power Delay Product”, 2009, World Academy of Science, Engineering and Technology.
[11]Ladner R, Fischer M,” Parallel prefix computation “, J.ACM, vol.27, no. 4, pp 831-838, Oct.1980.