International Journal of Engineering and Manufacturing (IJEM)
IJEM Vol. 8, No. 5, 8 Sep. 2018
Cover page and Table of Contents: PDF (size: 952KB)
Design and Implementation of a DDR2 SDRAM Controller for Audio Data on a Reconfigurable Platform
Full Text (PDF, 952KB), PP.32-48
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Author(s)
Arun Tigadi
1,*
Hansraj Guhilot
2
Index Terms
DDR2 SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), Audio Codec (coder-decoder), FPGA(Field Programmable Gate Array), UART(Universal Asynchronous Receiver and Transmitter)
Abstract
Multimedia applications play a very important role in the field of VLSI design and embedded systems. They need a large amount of memory storage with higher bandwidth and higher speed. To overcome this hazard, a memory controller is required. A memory controller is a device that stores the data and gives it back whenever required. Real-time recording of an audio data and finally storing it without losing the data is a difficult task. This paper describes the usage of Double Data Rate Synchronous Dynamic Random Access memory controller for storing the audio data. The design uses finite state machine (FSM) architecture that is developed for testing of this algorithm. Audio codec device is used for the conversion of analog data into digital and vice versa. The tool used to simulate this design is Xilinx ISE design suite. The hardware used to synthesize this design is FPGA Spartan-3 kit.
Cite This Paper
Arun Tigadi, Hansraj Guhilot,"Design and Implementation of a DDR2 SDRAM Controller for Audio Data on a Reconfigurable Platform", International Journal of Engineering and Manufacturing(IJEM), Vol.8, No.5, pp.32-48, 2018. DOI: 10.5815/ijem.2018.05.04
Reference
[1]Suyog V Pande, Prashant D Bhirange ‘Simulink based Low Power Mpeg-4 AAC Audio Encoder and Decoder’ IEEE ICCSP 2015 conference.
[2]Design of a TLM NAND Flash Controller Model for Audio Real-Time Applications M. Gianfelici; M. Conti; M. Caldari; F. Ripa 2015 12th International Workshop on Intelligent Solutions in Embedded Systems (WISES).
[3]Optimized FPGA-based DDR2 SDRAM controller Jian Qituo; Liu Liansheng; Peng Yu; Liu Datong 2013 IEEE 11th International Conference on Electronic Measurement & Instruments.
[4]An innovative design of the DDR/DDR2 SDRAM compatible controller Darshan Makam; H. V Jayashree International Conference on Nanoscience, Engineering and Technology (ICONSET 2011) Year: 2011.
[5]ZHUO L, DU G M, ZHANG D L, et al. Design and Implementation of DDR2 Wrapper for Cluster-Based MPSoC[C]. 2010 International Conference on Anti-Counterfeiting, Security, and Identification, 2010: 60-62.
[6]Benny Akesson, Kees Goossens and Markus Ringhofer published a paper ‘A Predictable SDRAM Memory Controller.’
[7]www.micron.com
[8]https://en.wikipedia.org/wiki/AC%2797
[9]https://en.wikipedia.org/wiki/DDR2_SDRAM
[10]www-inst.eecs.berkeley.edu
[11]https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/edk_ctt.pdf
[12]https://www.micron.com/~/media/documents/products/datasheet/.../512mbddr2.df
[13]Prof. Arun.S.Tigadi1, Padmashree. G International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering (An ISO 3297: 2007 Certified Organization)Vol. 5, Issue 8, August 2016 Design and Implementation of Memory Controller for Real-Time Video Acquisition using DDR3 SDRAM
[14]Mayankagr.in/images/matlab_tutorial.pdf
[15]Mani Shankar Anand, Barjeev Tyagi,"Design and Implementation of Fuzzy Controller on FPGA", IJISA, vol.4, no.10, pp.35-42, 2012.
[16]Sachin Raghav, Rinkesh Mittal,"Implementation of Fast and Efficient Mac Unit on FPGA", International Journal of Mathematical Sciences and Computing(IJMSC), Vol.2, No.4, pp.24-33, 2016.DOI: 10.5815/ijmsc.2016.04.03
[17]Shiraz Afzal, Farrukh hafeez, Muhammad Ovais Akhter,"Single Chip Embedded System Solution: Efficient Resource Utilization by Interfacing LCD through Softcore Processor in Xilinx FPGA", IJIEEB, vol.7, no.6, pp.23-27, 2015. DOI: 10.5815/ijieeb.2015.06.04