R.Varatharajan; Lekha R.

A Low Power BIST TPG for High Fault Coverage

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Author(s)

R.Varatharajan ^1,* Lekha R. ²

1. S.M.K Fomra Institute of Technology,Chennai, India

2. Srivenkateswara College of engineering and technology

* Corresponding author.

DOI: https://doi.org/10.5815/ijieeb.2012.04.03

Received: 13 May 2012 / Revised: 5 Jun. 2012 / Accepted: 1 Jul. 2012 / Published: 8 Aug. 2012

Index Terms

Built-in self-test (BIST), switching activity, low power testing, test pattern generator

Abstract

A low hardware overhead scan based BIST test pattern generator (TPG) that reduces switching activities in circuit under test (CUTs) and also achieve very high fault coverage with reasonable length of test sequence is proposed. When the proposed TPG used to generate test patterns for test-per-scan BIST, it decreases the number transitions that occur during scan shifting and hence reduces the switching activity in the CUT. The proposed TPG does not require modifying the function logic and does not degrade system performance. The proposed BIST comprised of three TPGs: Low transition random TPG (LT-RTPG), 3-weight weighted random BIST (3-weight ERBIST) and Dual-speed LFSR (DS-LFSR). Test patterns generated by the LT-RTPG detect the easy-to-detect faults and remain the undetected faults can be detected by the WRBIST. The 3-weight WRBIST is used to reduce the test sequence lengths by improving detection probabilities of random pattern resistant faults (RPRF). The DS-LFSR consists of two LFSR's, slow LFSR and normal–speed LFSR. The DS-LFSR lowers the transition density at their circuit inputs.

Cite This Paper

R.Varatharajan, Lekha R., "A Low Power BIST TPG for High Fault Coverage", International Journal of Information Engineering and Electronic Business(IJIEEB), vol.4, no.4, pp.19-24, 2012. DOI:10.5815/ijieeb.2012.04.03

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International Journal of Information Engineering and Electronic Business (IJIEEB)