International Journal of Information Engineering and Electronic Business (IJIEEB)

IJIEEB Vol. 4, No. 4, Aug. 2012

Cover page and Table of Contents: PDF (size: 136KB)

Table Of Contents

REGULAR PAPERS

Research Issues in Personalization of Mobile Services

By Muhammad Asif John Krogstie

DOI: https://doi.org/10.5815/ijieeb.2012.04.01, Pub. Date: 8 Aug. 2012

Personalization is gaining more importance with the increase of mobile and community services. Provision of personalized mobile services can help to meet the individual needs at a time and place when and where a user needs it. Mobile services should be designed to be usable and useful to realize the benefits of personalization. It is not an easy task to satisfy the individual's goals or needs. Currently, mobile services are designed either using a client side or server- side approach. At the same time, it is raising different research issues ranging from technological to security or privacy concerns. In this work, we described the current research and development in the area of personalization of mobile services. The objective of this paper is to analyze which design approach is suitable for the personalization of mobile services. Finally, we have discussed issues and challenges related to client-side personalization vs server-side personalization and the recent trends in personalization of mobile services.

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WebSEReleC – Optimized Web Implementation of SEReleC Using Google

By Vishwas J Raval Padam Kumar

DOI: https://doi.org/10.5815/ijieeb.2012.04.02, Pub. Date: 8 Aug. 2012

The World Wide Web has immense resources for all kind of people for their specific needs. Searching on the Web using search engines such as Google, Bing, Ask have become an extremely common way of locating information. Searches are factorized by using either term or keyword sequentially or through short sentences. The challenge for the user is to come up with a set of search terms/keywords/sentence which is neither too large (making the search too specific and resulting in many false negatives) nor too small (making the search too general and resulting in many false positives) to get the desired result. No matter, how the user specifies the search query, the results retrieved, organized and presented by the search engines are in terms of millions of linked pages of which many of them might not be useful to the user fully. In fact, the end user never knows that which pages are exactly matching the query and which are not, till one check the pages individually. This task is quite tedious and a kind of drudgery. This is because of lack of refinement and any meaningful classification of search result. Providing the accurate and precise result to the end users has become Holy Grail for the search engines like Google, Bing, Ask etc. There are number of implementations arrived on web in order to provide better result to the users in the form of DuckDuckGo, Yippy, Dogpile etc. This research proposes development of a meta-search engine, called WebSEReleC (Web-based SEReleC) that provides an interface for refining and classifying the search engines' results so as to narrow down the search results in a sequentially linked manner resulting in drastic reduction of number of pages using power of Google.

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A Low Power BIST TPG for High Fault Coverage

By R.Varatharajan Lekha R.

DOI: https://doi.org/10.5815/ijieeb.2012.04.03, Pub. Date: 8 Aug. 2012

A low hardware overhead scan based BIST test pattern generator (TPG) that reduces switching activities in circuit under test (CUTs) and also achieve very high fault coverage with reasonable length of test sequence is proposed. When the proposed TPG used to generate test patterns for test-per-scan BIST, it decreases the number transitions that occur during scan shifting and hence reduces the switching activity in the CUT. The proposed TPG does not require modifying the function logic and does not degrade system performance. The proposed BIST comprised of three TPGs: Low transition random TPG (LT-RTPG), 3-weight weighted random BIST (3-weight ERBIST) and Dual-speed LFSR (DS-LFSR). Test patterns generated by the LT-RTPG detect the easy-to-detect faults and remain the undetected faults can be detected by the WRBIST. The 3-weight WRBIST is used to reduce the test sequence lengths by improving detection probabilities of random pattern resistant faults (RPRF). The DS-LFSR consists of two LFSR's, slow LFSR and normal–speed LFSR. The DS-LFSR lowers the transition density at their circuit inputs.

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Web Portal Analysis of Asian Region Countries

By Subhash Chander Ashwani Kush

DOI: https://doi.org/10.5815/ijieeb.2012.04.04, Pub. Date: 8 Aug. 2012

The number of online services provided by Government and private sectors is increasing these days. On the same pattern various countries have their own portals to provide basic services to the citizens and other people of the world. Analysis of portals in Asia is the main theme of the paper. There are various indicators or attributes necessary for the implementation of e-services .Some of the indicators may be frequency of use of services, number of users, visitors, site hits, searchable option, accessibility, language option, performance, functionality, broken links, traffic analysis, and feedback. Out of these metrics taken into consideration here are Traffic analysis, feedback, accessibility, security and language option. The countries taken into consideration are India, China and Pakistan. Web portals of these countries will be analyzed in detail.

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An Analogous Computation of Different Techniques for The Digital Implementation of Inverter and NAND Logic Gates

By I.Hameem Shanavas M. Brindha V.Nallusamy

DOI: https://doi.org/10.5815/ijieeb.2012.04.05, Pub. Date: 8 Aug. 2012

Feature size reduction in microelectronic circuits has been an important contributing factor to the dramatic increase in the processing power of computer arithmetic circuits. However, it is generally accepted that MOS based circuits cannot be reduced further in feature size due to fundamental physical restrictions. Therefore, several emerging technologies are currently being investigated. Nano devices offer greater scaling potential than MOS as well as ultra low power consumption. Nano devices display a switching behaviour that differs from traditional MOS devices. This provides new possibilities and challenges for implementing digital circuits using different techniques like CNTFET,SET, FinFET etc. In this work the design of Inverter and Nand gate using CNT, SET and FinFET has been analyzed elaborately with its own advantageous of the mentioned techniques.

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Memetic Programming Approach for Floorplanning Applications

By R.Varatharajan Muthu Senthil Perumal Sankar

DOI: https://doi.org/10.5815/ijieeb.2012.04.06, Pub. Date: 8 Aug. 2012

Floorplanning is a very crucial step in modern VLSI design. It dominates the top level spatial structure of a chip and initially optimizes the interconnections. Thus a good floorplan solution among circuit modules definitely has a positive impact on the placement, Routing and even manufacturing. In this paper the classical floorplanning that usually handles only block packing to minimize silicon rate, so modern floorplanning could be formulated as a fixed outline floorplanning. It uses some algorithms such as B-TREE representation, simulated annealing and adaptive fast simulated annealing, comparing above three algorithms the better efficient solution came from adaptive fast simulated annealing, it's leads to faster and more stable convergence to the desired floorplan solutions, but the results are not an optimal solution, to get an optimal solution it's necessary to choose effective algorithm. Combining global and local search is a strategy used by many optimization approaches. Memetic algorithm is an evolutionary algorithm that includes one or more local search phases within its evolutionary cycle. The algorithm combines a hierarchical design technique, genetic algorithms, constructive techniques and advanced local search to solve VLSI floorplanning problem.

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Design Of High Performance Reconfigurable Routers Using Fpga

By R.Parthasarathi P.Karunakaran S.Venkatraman T.R.DineshKumar I.Hameem Shanavas

DOI: https://doi.org/10.5815/ijieeb.2012.04.07, Pub. Date: 8 Aug. 2012

Network-on-chip(NoC) architectures are emerging for the highly scalable, reliable, and modular on-chip communication infrastructure platform. The NoC architecture uses layered protocols and packet-switched networks which consist of on-chip routers, links, and network interfaces on a predefined topology. In this Project, we design network-on-chip which is based on the Cartesian network environment. This project proposes the new Cartesian topology which is used to reduce network routing time, and it is a suitable alternate to network design and implementation. The Cartesian Network-On-Chip can be modeled using Verilog HDL and simulated using Modelsim software.

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Data-Centric Enterprise Architecture

By Zeinab Rajabi Maryam Nooraei Abade

DOI: https://doi.org/10.5815/ijieeb.2012.04.08, Pub. Date: 8 Aug. 2012

Enterprises choose Enterprise Architecture (EA) solution, in order to overcome dynamic business challenges and in coordinate various enterprise elements. In this article, a solution is suggested for the Enterprise Architecture development. The solution focuses on architecture data in the Enterprise Architecture development process. Data-centric architecture approach is preferred product-centric architecture approach. We suggest using Enterprise Ontology (EO) as context for collecting architecture data; Enterprise Ontology enhances quality of architecture data and lead to effective architecture results for decision-making. First, Enterprise is modeled using the ontology. Then how collecting Enterprise Architecture data based on the Enterprise Ontology is explained. Finally, the results and advantages of the solution are demonstrated.

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