International Journal of Information Engineering and Electronic Business (IJIEEB)
IJIEEB Vol. 6, No. 3, 8 Jun. 2014
Cover page and Table of Contents: PDF (size: 899KB)
Simulation and Optimization of VHDL code for FPGA-Based Design using Simulink
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Author(s)
Naresh Grover
1,*
M.K.Soni
1
Index Terms
Modelsim, Simulink, Simulation, Optimization
Abstract
Simulations and prototyping have been a very important part of the electronics industry since a very long time. In recent years, FPGA's have become increasingly important and have found their way into all kind of digital system design This paper presents a novel, easy and efficient approach of implementation and verification of VHDL code using Simulink and then to regenerate the optimized VHDL code again using Simulink. The VHDL code written for the complicated digital design of 32-bit floating point arithmetic unit has been synthesized on Xilinx, verified and simulated on Simulink. The same VHDL code in Modelsim was optimized using this approach and the optimized code so generated by Simulinkhas also been synthesized to compare the results. Power dissipations for both synthesized designs using Xilinx Power Estimator were also extracted for comparison.
Cite This Paper
Naresh Grover, M.K.Soni, "Simulation and Optimization of VHDL code for FPGA-Based Design using Simulink", International Journal of Information Engineering and Electronic Business(IJIEEB), vol.6, no.3, pp.22-27, 2014. DOI:10.5815/ijieeb.2014.03.04
Reference
[1]Shi, C., Hwang, J., McMillan, S., Root, A., and Singh, V.,"A System Level Resource Estimation Tool for FPGAs",International Conference on Field Programmable Logic and Applications (FPL), 2004.
[2]Xilinx Inc., Synthesis and Simulation Design Guide. June 2008.
[3]P. Garrault and B. Philofsky, "HDL Coding Practices to Accelerate Design Performance," Xilinx White Paper, wp231, pp. 1–22, Jan 2006
[4]F. Li, D. Chen, L. He, and J. Cong, "Architecture evaluation for power–efficient FPGAs," Proc.OftheACM/SIGDAInternational.Symposium onFieldProgrammable Gate Arrays, Feb. 2003,pp.175–184.
[5]Y. Zhang, J. Roivainen, and A. Mammela, "Clock–Gating in FPGAs: ANovel and Comparative Evaluation," Proc. of 9th EUROMICRO Conf.on Digital System Design (DSD'06), 2006, pp. 584–590.
[6]R. Manohar, "Reconfigurable asynchronous logic," Proc. of IEEE Custom Integrated Circuits Conf., Sept. 2006, pp. 13–20.
[7]ActelCorp.,"Designing for low power in ActelAntifuseFPGAs,"Application Note AC140, pp. 1–8, Sept. 2000.
[8]Naresh Grover, M.K.Soni," Design of FPGA-based 32-bit Floating Point Arithmetic Unit and verification of its VHDL code using MATLAB" IJIEEB, MECS pp 1-14, Jan 2014.
[9]Simulink HDL Coder 1; User's Guide; 2006-2010 by the MathWorks, Inc.
[10]Hikmat N. Abdullah and Hussein A. Hadi "Design and Implementation of FPGA Based Software Defined Radio Using Simulink HDL Coder". Engineering and Technology Journal, Iraq, ISSN 1681-6900 01/2010; Vol.28 (No.23):pp.6750-6767.
[11]R. Nanda, C.H. Yang and D. Markovic "DSP Architecture Optimization in MATLAB/Simulink Environment" in Proceedings International Symposium VLSI Circuits June 2008 pp 192-193.