International Journal of Information Engineering and Electronic Business (IJIEEB)
IJIEEB Vol. 6, No. 5, 8 Oct. 2014
Cover page and Table of Contents: PDF (size: 1263KB)
Implementation of Particle Swarm Optimization Algorithm in VHDL for Digital Circuits Optimization
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Author(s)
Garima Grover
1,*
Ila Chaudhary
2
Index Terms
Digital combinational circuits, VHDL, Particle Swarm Optimization, Search Space, Human methods
Abstract
In order to accomplish the targets of specified levels for reducing the hardware requirements of digital systems, innovative techniques are required to be implemented either at the device level, architectural level or gate level designs. In this paper one of the evolutionary techniques i.e. Particle Swarm Optimization Algorithm has been used to optimize digital circuits at the gate level on VHDL platform to draw an automatic, generalised and reliable technique to find optimum solutions with reduced gate count for the designing of digital systems.
Cite This Paper
Garima Grover, Ila Chaudhary, "Implementation of Particle Swarm Optimization Algorithm in VHDL for Digital Circuits Optimization", IJIEEB, vol.6, no.5, pp.16-21, 2014. DOI:10.5815/ijieeb.2014.05.03
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