In order to accomplish the targets of specified levels for reducing the hardware requirements of digital systems, innovative techniques are required to be implemented either at the device level, architectural level or gate level designs. In this paper one of the evolutionary techniques i.e. Particle Swarm Optimization Algorithm has been used to optimize digital circuits at the gate level on VHDL platform to draw an automatic, generalised and reliable technique to find optimum solutions with reduced gate count for the designing of digital systems.