International Journal of Image, Graphics and Signal Processing (IJIGSP)
IJIGSP Vol. 11, No. 6, 8 Jun. 2019
Cover page and Table of Contents: PDF (size: 542KB)
Simulation of a Ballistic SW-CNTFET with Coaxial Geometry: Numerical Approach to Determine the impact of Gate Oxide Thickness on the Performance
Full Text (PDF, 542KB), PP.27-34
Views: 0 Downloads: 0
Author(s)
Debashish Pal
1,*
Soumee Das
2
Index Terms
Carrier Injection Velocity, Chirality, CNTFET, DIBL, Drive Current, Natori Approach, Short Channel Effect, Sub-threshold Swing, Tight Binding Energy, Trans-conductance
Abstract
Carbon Nanotube Field Effect Transistors (CNTFETs) are being proposed as candidates for next-generation integrated circuit technology replacing conventional MOSFET devices. It is a suitable nanoelectronic device which is used for high speed and low power design applications which include analog and digital circuits. In this paper, a single wall carbon nanotube field effect transistor (SW-CNTFET) with a coaxial structure in the ballistic regime has been studied and its performance parameters discussed. Numerical simulations were performed based on Natori approach. The various device metrics in consideration are drive current (Ion), Ion/Ioff ratio, output conductance (gd), trans-conductance (gm), gain, carrier injection velocity, sub-threshold swing and drain induced barrier lowering (DIBL). In particular, the influences of gate oxide thickness on the short-channel effects are presented in detail. Also, the dependence of sub-threshold swing and DIBL on the gate control parameter has been discussed.
Cite This Paper
Debashish Pal, Soumee Das, "Simulation of a Ballistic SW-CNTFET with Coaxial Geometry: Numerical Approach to Determine the impact of Gate Oxide Thickness on the Performance", International Journal of Image, Graphics and Signal Processing(IJIGSP), Vol.11, No.6, pp. 27-34, 2019. DOI: 10.5815/ijigsp.2019.06.04
Reference
[1]H. Liu, A.T. Neal, P.D. Ye, “Channel length scaling of MoS2 MOSFETs”, ACS Nano, vol. 6, no. 10, pp. 8563–8569, 2012.
[2]D.A. Antoniadis, I. Aberg, C.N. Chléirigh, et al. “Continuous MOSFET performance increase with device scaling: the role of strain and channel material innovations”, IBM J. Res. Dev., vol. 50, no. 4, pp. 363–376, 2006.
[3]J.W.G. Wilder, L.C. Venema, A.G. Rinzler, R.E. Smalley, C. Dekker, “Electronic structure of atomically resolved carbon nanotubes”, Nature, vol. 391, pp. 59-62, 1998.
[4]K. Boucart, A.M. Ionescu, “Double-gate tunnel FET with high-k gate dielectric”, IEEE Trans. Electron Devices, vol. 54, no. 7, pp. 1725–1733, 2007.
[5]J. Robertson, “High dielectric constant gate oxides for metal oxide Si transistors”, Rep. Prog. Phys., vol. 69, no. 2, pp. 327-396, 2005.
[6]S. Thompson, “MOS scaling: transistor challenges for the 21st century”, Intel Technol. J., vol. 398, pp. 1–9, 1998.
[7]D. Dass, R. Prasher, R. Vaid, “Impact of Scaling Gate Insulator Thickness on the Performance of Carbon Nanotube Field Effect Transistors (CNTFETs)”, Journal of Nano- and Electronic Physics, vol. 5, no. 2, pp. 1-6, 2013.
[8]J.K. Saha, N. Chakma, M. Hasan, “Impact of channel length, gate insulator thickness, gate insulator material, and temperature on the performance of nanoscale FETs”, Journal of Computational Electronics, 2018.
[9]K. Natori, “Ballistic metal‐oxide‐semiconductor field effect transistor”, J. Appl. Phys., vol. 76, no. 8, 1994.
[10]F. Leonard, “Physics of Carbon Nanotube Devices”, William Andrew Inc.: USA, 2009.
[11]R. Sahoo, R. R. Mishra, “Simulations of Carbon Nanotube Field Effect Transistors”, International Journal of Electronic Engineering Research, vol. 1, no. 2, pp. 117–125, 2009.
[12]J. Guo, M. Lundstrom, S. Datta, “Performance projections for ballistic carbon nanotube field-effect transistors”, Applied Physics Letters, vol. 80, no. 17, 2002.
[13]D. Dass and R. Vaid, “Impact of SWCNT Band Gaps on the Performance of a Ballistic Carbon Nanotube Field Effect Transistors (CNTFETs)”, Journal of Nano- and Electronic Physics, vol. 9, no. 4, pp. 1-5, 2017.
[14]Q. Chen, B. Agrawal, J. Meindl, “A comprehensive analytical sub-threshold swing (S) model for double-gate MOSFETs”, IEEE Trans. Electron Devices, vol. 49, no. 6, pp. 1086–1090, 2002.