International Journal of Image, Graphics and Signal Processing(IJIGSP)
ISSN: 2074-9074 (Print), ISSN: 2074-9082 (Online)
Published By: MECS Press
IJIGSP Vol.2, No.2, Dec. 2010
A New Adder Theory Based on Half Adder and Implementation in CMOS Gates
Full Text (PDF, 448KB), PP.11-17
This paper proposes a new theory of adder and its basic structure. The new adder of asynchronous structure constructed by half adders, called Parallel Feedback Carry Adder (PFCA) as its carry mode is parallel feedback. In theory, the area consumption of n-bit PFCA is close to O(n) and the average length of carry chain is O(log n). A CMOS gate implementation scheme is implemented. HSPICE simulation results show that PFCA has obvious advantages over RCA, CLA, CSeA in speed and area, especially when n is bigger.
Cite This Paper
Zhanfeng Zhang,Liyuan Sheng,Wenming Jiang,Shuai Tong,Hua Cao, "A New Adder Theory Based on Half Adder and Implementation in CMOS Gates", IJIGSP, vol.2, no.2, pp.11-17, 2010.
D. Goldberg, “Computer arithmetic”, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, 1990.
O.J.Bedrij, “Carry-select adder”, IRE Transactions on Electronic Computer, vol. EC-11, Jun.1962.pp.340-346.
O. L. MacSorley, “High-speed arithmetic in binary adders”, IRE proceedings, vol.49, 1961.pp.67-91.
S. Tuttini, “Optimal group distribution in carry-skip adders”, Proceedings of the 9th symposium on computer arithmetic, step. 1989. pp.96-103.
A.J.Martin, “Asynchronous data paths and the design of an asynchronous adder”, Formal Method in system Design, 1(1):119-137.July.1992.
J.D. Garside,“A CMOS VLSI Implementation of an asynchronous ALU”, Proceeding of the IFIP Working Conference on Asynchronous Design Methodologies, Manchester, England (1993).
Cheng F C,Unger S H,Theobald M. Self-timed carry-lookahead adders[J]. IEEE Transactions on Computers, 2000,49(7):659~672.
Cheng F C. Practical design and performance evaluation of completion detection circuits [A]. Computer Design: VLSI in computers and processors[C]. California: IEEE Computer Society, 1998.354~359.
Singh R P P, Kumar P, Singh B. Performance analysis of fast adders using VHDL[A].International conference on advances in recent technologies in Communication and Computing[C]. California: IEEE Computer Society, 2009.189~193.
Briley B E. Some new results on average worst case carry [J]. IEEE Transactions on Computers.1973,22(5): 459~463.
Burks A W,Goldstine H H, Neumann J V. Preliminary discussion of the logical design of an electronic computing instrument [M]. New Jersey: Institute for Advanced Study, 1946.34~79.
Kinniment D J.An evaluation of asynchronous addition [J].IEEE Transactions VLSI Systems.1996. 4(1): 137~140.
Franklin M A,Pan T.Clocked and asynchronous instruction pipelines[A].Proceedings of the 26th Annual International Symposium on Micro architecture [C]. California: IEEE Computer Society Press, 1993.177 ~184.
Vasefi F, Abid Z. 10-transistor 1-bit adders for n-bit parallel adders [A].The 16th International Conference on Microelectronics [C]. California: IEEE Computer Society Press, 2004.174 ~177.
Vesterbacka M.A 14-transistor CMOS full adder with full voltage-swing nodes[A].IEEE Workshop on Signal Processing Systems[C].Taipei Design and Implementation.1999.713 ~ 722.
Navia K, Foroutan V, Azghadi M R,et al. A novel low-power full-adder cell with new technique in designing logical gates based on static CMOS inverter [J].Microelectronics Journal, 2009.40: 1441~1448.