International Journal of Image, Graphics and Signal Processing (IJIGSP)
IJIGSP Vol. 8, No. 8, 8 Aug. 2016
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Area Reduction in Redundancy Module for an ECC Based Fault Tolerance in Digital Filters
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Author(s)
Jyoti Saini
1,*
Harpal Singh
1
Index Terms
Fault tolerance, ECC, Xilinx, Slices, LUT, Digital filters
Abstract
Due to the wide usage of digital filters in communication systems, reliability and area has to be considered and deficiency tolerant channel usage are required. Throughout the decades, there are number of techniques that have been proposed to achieve fault tolerance. As the number of parallel filters are increasing in any digital device, the redundancy module should also be small in size. In this paper, a simple technique of constant multiplication reduction method is introduced in the Error Correction Codes (ECC) based parallel filters in order to reduce the size of the redundant module. Main agenda is to reduce the size of the redundant module by not affecting the functionalityof the system. The proposed scheme is coded in HDL and simulation results are obtained by using Xilinx 12.1i. The presented result shows that the slices can be reduced and hence the size. As a result of reduction in size, the optimization of area can also be concluded.
Cite This Paper
Jyoti Saini, Harpal Singh,"Area Reduction in Redundancy Module for an ECC Based Fault Tolerance in Digital Filters", International Journal of Image, Graphics and Signal Processing(IJIGSP), Vol.8, No.8, pp.24-29, 2016. DOI: 10.5815/ijigsp.2016.08.04
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