International Journal of Modern Education and Computer Science (IJMECS)
IJMECS Vol. 10, No. 4, 8 Apr. 2018
Cover page and Table of Contents: PDF (size: 882KB)
Design of an Efficient Current Mode Full-Adder Applying Carbon Nanotube Technology
Full Text (PDF, 882KB), PP.43-50
Views: 0 Downloads: 0
Author(s)
Index Terms
Full-adder, current mode, nanotechnology, CNTFET, majority function
Abstract
In this article a new design of a current mode full-adder is proposed through the field effect transistors based on carbon nanotubes. The outperformance of the current mode full-adder constructed by CNTFET compared to that of constructed by CMOS is observable in the simulation and comparisons. This circuit operates based on triple input majority function. The simulation is run by HSPICE software according to the model proposed in Stanford University for CNTFETs at 0.65 V power supply voltage. The proposed circuit outperforms compared to the previous current mode full-adders in terms of speed, accuracy and PDP.
Cite This Paper
Parisa Nejadzadeh, Mohammad Reza Reshadinezhad, " Design of an Efficient Current Mode Full-Adder Applying Carbon Nanotube Technology", International Journal of Modern Education and Computer Science(IJMECS), Vol.10, No.4, pp. 43-50, 2018. DOI:10.5815/ijmecs.2018.04.06
Reference
[1]P. Bhattacharyya, B. Kundu, S. Ghosh, V. Kumar, A. Dandapat, “Performance analysis of a low-power high-speed hybrid 1-bit full adder circuit,” IEEE Transactions on very large scale integration (VLSI) systems, 23(10), pp. 2001-2008, 2015.
[2]M. R. Reshadinezhad, M. H. Moaiyeri, K. Navi, “An Energy-Efficient Full Adder Cell Using CNFET Technology,” IEICE transactions on electronics, NO.95, Vol.4, pp. 744-751, 2012.
[3]S. A. Ebrahimi, M. R. Reshadinezhad, A. Bohlooli, M. Shahsavari, “Efficient CNTFET-based design of quaternary logic gates and arithmetic circuits,” Microelectronics Journal, Volume 53, Pp. 156-166, July 2016.
[4]H. T. Bui, Y. Jiang, “Design and analysis of low-power 10-transistor full adders using XOR-XNOR gates,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process, 49 (1), pp. 25-30, 2002.
[5]S. Goel, A. Kumar, M. A. Bayoumi, “Design of robust, energy efficient full adders for deepsubmicrometer design using hybrid-CMOS logic style,” IEEE Transactions on Very Large Scale Integration Systems, 14(12), pp. 1309-1321, 2006.
[6]M. R. Reshadinezhad, N. Charmchi, K. Navi, “Design and Implementation of a Three-operand Multiplier through Carbon Nanotube Technology,” International Journal of Modern Education and Computer Science, Vol. 7, Iss. 9, pp. 44-51, Sep 2015.
[7]Z. H. Kong, K. S. Yeo, C. H. Chang, “Design of an area-efficient CMOS multiple-valued current comparator circuit,” IEEE Proc.-Circuits Devices Syst, Vol.152 (2), pp. 151-158, 2005.
[8]J. T. Butler, “Multiple-valued logic: Examining its use in ultra-high speed computation,” IEEE Potentials, 14 (2), pp. 11-14, 1995.
[9]A. G. Delavar, K. Navi, O. Hashemipour, “High Speed Full Swing Current Mode BiCMOS Logical Operators,” IJE Transactions, Vol 20 (3), pp. 211-220, 2007.
[10]N. Weste, D. Harriss, CMOS VLSI Design, 3rd ed., Addison Wesley, 2005.
[11]M. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits, Second Edition, Upper Saddle River, New Jersey: Prentice-Hall, 2003.
[12]S. Rahbar Arabani, M. R. Reshadinezhad, M. Hagparast, “ Design of a Parity preserving Reversible Full Adder/Subtractor Circuit,” International Journal of Computational Intelligence Studies, Vol. 7, No. 1, pp. 19-32, 2018.
[13]G. Gho, Y. B. Kim, F. Lombardi, “Performance evaluation of CNFET-base logic gates,” Proc. IEEE International instrumentation and measurement technology conference. Pp. 909-912, 2009.
[14]F. Sharifi, M. H. Moaiyeri, K.Navi, “A Novel Quaternary Full Adder Cell Based on Nanotechnology,” I.J. Modern Education and Computer Science, Vol.7, No.3, pp. 19-25, 2015.
[15]M. H. Moaiyeri , R. F. Mirzaee, K. Navi, A. Momeni, “Design and analysis of a high-performance CNFET-based Full Adder,” International Journal of Electronics, 99(1), pp. 113-130, 2012.
[16]R. Saito, G. Dresselhaus, M. S. Dresselhaus, Physical Properties of carbon nanotubes, imperial college press, London, 1998.
[17]P. Avouris, Z. Chen, V. Perebeinos, “Carbon-based electronics,” Nature Nanotechnology 2, v2/n10, pp. 605-615, 2007.
[18]R. Martel, T. Schmidt, H. R. Shea, T. Hertel, Ph. Avouris, “Single and multi-wall carbon nanotube field-effect transistors,” Applied Physics Letters, Vol.73(17), pp. 24-47, 1998.
[19]R. Saito, T. Takeya, T. Kimura, G. Dresselhaus, M. S. Dresselhaus, “Raman intensity of single-wall carbon nanotubes,” Phys. Rev.B, Volume 57, Issue 7, pp. 41-45, 1998.
[20]M. Ahmadi, M. R. Reshadinezhad, “A New High Speed 2n−1 Modular Adder Based on Carbon Nano Tube Field Effect Transistors,” Journal of and Optoelectronics, Vol. 12, pp. 1-8, July 2017.
[21]Y. B. Kim, F. Lombardi, “A Novel Design Methodology to Optimize the Speed and Power of the CNTFET Circuits,” 52nd IEEE International Midwest Symposium on Circuits and Systems, pp. 1130-1133, 2009.
[22]S. Heinze, J. Tersoff, R. Martel, V. Derycke, J. Appenzeller, P. Avouris, “Carbon nanotubes as Schottky barrier transistors,” Physical Review Letters, 89(10), pp. 106801, 2002.
[23]K. Navi, R. Zabihi, M. Haghparast, T. Nikobin, “A Novel Mixed Mode Current and Dynamic Voltage Full adder,” World Applied Sciences Journal, Vol.4, pp. 289 -294, 2008.
[24]S. Wairya, R. K. Nagaria, S. Tiwati, “New Design Methodologies for High Speed Mixed- Mode Full Adder Circuit,” International Journal of VLSI and Communication Systems (VLSICS), AIRCC Publication, vol. 2, no. 2, pp. 78-98, 2011.
[25]K. Navi, M. H. Moaiyeri, F. R. Mirzaee, O. Hashemipour, B. Mazloom Nezhad, “Two new low-power Full Adders based on majority-not gates,” Microelectronics Journal, Vol. 40, pp. 126-130, 2009.
[26]S. R. P. Sinha, N. Tiwari, “Design and Analysis of Dynamic Current Mode Full Adder with reduced Power and Delay,” International Journal of Science and Research (IJSR), ijsr.net, Volume 4 Issue 11, pp. 2383 – 2388, 2015.
[27]F. Sharifi, A. Momeni, K. Navi, “CNFET BASED BASIC GATES AND A NOVEL FULLADDER CELL,” International Journal of VLSI design & Communication Systems (VLSICS), Vol.3, No.3, pp. 11, 2012.