INFORMATION CHANGE THE WORLD

International Journal of Modern Education and Computer Science (IJMECS)

ISSN: 2075-0161 (Print), ISSN: 2075-017X (Online)

Published By: MECS Press

IJMECS Vol.3, No.3, Jun. 2011

Design and Implementation of a Low Power RSA Processor for Smartcard

Full Text (PDF, 207KB), PP.8-14


Views:147   Downloads:4

Author(s)

Zhen Huang,Shuguo Li

Index Terms

Montgomery algorithm; Chinese Remainder Theory(CRT); operand isolation; clock gating

Abstract

Power consumption limits the application of public key cryptosystem in portable devices. This paper proposes a low power design of 1,024-bit RSA. In algorithm, the Chinese Remainder Theorem (CRT) and an improved Montgomery algorithm are selected to decrease the computation of RSA. In architecture and circuit, the operand isolation technique is applied to avoid unnecessary flip-flops of the combinational logic, and the clock gating technique is used to reduce the power dissipation of the registers. The proposed design is functionally verified on Altera FPGA EP2C8Q208C8N device. With SMIC 0.18m CMOS process, the Synopsys synthesizing result shows that the area and the critical path are 7.1k gates and 5.3ns respectively, while the power is 2.56mW and the throughput can reach 49 kbps. Thus the proposed design requires lower power than previous designs.

Cite This Paper

Zhen Huang,Shuguo Li,"Design and Implementation of a Low Power RSA Processor for Smartcard", IJMECS, vol.3, no.3, pp.8-14, 2011.

Reference

[1]R. L. Rivest, A. Shamir and L. A. Adleman, “Method for obtain digital signatures and public-key cryptosystems,” Communications of the ACM, 1978, 21(2): 120-126.

[2]P. L. Montgomery, “Modular mulbtiplication without trial division,” Mathematics of Computation, 1985, 44(170): 519-521.

[3]J. -J. Quisquater, C. Couvreur, “Fast decipherment algorithm for RSA public-key cryptosystem,” Electronics Letters, 1982, 18(21): 905-907.

[4]C. K. KoC, T. Acar, “Analyzing and comparing Montgomery multiplication algorithms,” [J]. IEEE Micro, 1996, 16(3): 26-33.

[5]Xiqing Yu, ASIC Design Practical Course (in Chinese), Zhejiang University Press, Hangzhou, China: Jan. 2007, pp. 229-280.

[6]Chingwei Yeh, En-Feng Hsu, Kai-Wen Cheng, Jinn-Shyan Wang, Nai-Jen Chang, “An 830mW, 586kbps, 1024-bit RSA chip design,” Processings of the Conference on Design, Automation and Test in Europe, Mar. 2006.

[7]Xinjian Zheng, Zexiang Liu, Bo Peng, “Design and implementation of an ultra low power RSA coprocessor,” WiCOM' 08. 4th International Conference on Wireless Communications, Networking and Mobile Computing, Oct. 2008. pp. 1-5.

[8]Wei Huang, Kaidi You, Suiyu Zhang, Jun Han, Xiaoyang Zeng, “Unified low cost crypto architecture accelerating RSA/SHA-1 for security processor,” ASICON'09. IEEE 8th International Conference on ASIC, Oct. 2009. pp. 151-154.

[9]Guanzhang Hu, Dianjun Wang, Applied Modern Algebra 3rd edition (in Chinese), Tsinghua University Press, Beijing, China: Jul. 2006, pp. 29-34.

[10]K. H. Rose, Elementary Number Theory and Its Application [M], Addison-Wesley, 1984.

[11]D. E. Kunth, The Art of Computer Programming: Semi-numerical Algorithms[M], Volume 2. Addison-Wesley, 3rd edition, 1998