International Journal of Modern Education and Computer Science (IJMECS)
IJMECS Vol. 5, No. 2, 8 Feb. 2013
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Enhancing Leakage Power in CPU Cache Using Inverted Architecture
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Author(s)
Index Terms
SRAM, Cache, Inverter, Dynamic power, Static power, CMOS
Abstract
Power consumption is an increasingly pressing problem in modern processor design. Since the on-chip caches usually consume a significant amount of power so power and energy consumption parameters have become one of the most important design constraint. It is one of the most attractive targets for power reduction. This paper presents an approach to enhance the dynamic power consumption of CPU cache using inverted cache architecture. Our assumption tries to reduce dynamic write power dissipation based on number of ones and zeros in the in-coming cache block data using bit to indicate is the block is mostly one or zero. This architecture reduces the dynamic write power by 17 %. We use Proteus Simulator to test that proposed circuit and performed the experiments on a modified version of the cacti6.0 simulator.
Cite This Paper
Bilal A. Shehada, Ahmed M. Serdah, Aiman Abu Samra, "Enhancing Leakage Power in CPU Cache Using Inverted Architecture", International Journal of Modern Education and Computer Science (IJMECS), vol.5, no.2, pp.12-18, 2013. DOI:10.5815/ijmecs.2013.02.02
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