International Journal of Modern Education and Computer Science (IJMECS)
IJMECS Vol. 5, No. 5, 8 May 2013
Cover page and Table of Contents: PDF (size: 354KB)
Design and Development MIPS Processor Based on a High Performance and Low Power Architecture on FPGA
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Author(s)
Tina Daghooghi
1,*
Index Terms
High Performance, Low Power, FPGA, double edge register, Combinational Logic.
Abstract
This paper presents the design and development of a high performance and low power MIPS microprocessor and implementation on FPGA. In this method we for achieving high performance and low power in the operation of the proposed microprocessor use different methods including, unfolding transformation (parallel processing), C-slow retiming technique, and double edge registers are used to get even reduce power consumption. Also others blocks designed based on high speed digital circuits. Because of feedback loop in the proposed architecture C-slow retiming can enhance designs that contain feedback loops. The C-slow retiming is well-known for optimization and high performance technique, it automatically rebalances the registers in the proposed design. The proposed high performance microprocessor is modeled and verified using FPGA and simulation results. The proposed methods in microprocessor have been successfully synthesized and implemented in Quartus II 9.1 and Stratix II FPGA, to target device EP2S15F484C3, and power is analyzed with Xpower analyzer. Results demonstrate that the proposed method has high performance.
Cite This Paper
Tina Daghooghi, "Design and Development MIPS Processor Based on a High Performance and Low Power Architecture on FPGA", International Journal of Modern Education and Computer Science (IJMECS), vol.5, no.5, pp.49-59, 2013. DOI:10.5815/ijmecs.2013.05.06
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