International Journal of Modern Education and Computer Science (IJMECS)
IJMECS Vol. 7, No. 11, 8 Nov. 2015
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A Novel 4×4 Universal Reversible Gate as a Cost Efficient Full Adder/Subtractor in Terms of Reversible and Quantum Metrics
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Author(s)
Index Terms
Reversible logic, Quantum Cost, Full Adder/Subtractor cell, Low power design, Reversible metrics
Abstract
This paper proposes a new 4×4 reversible logic gate which is named as MOG. Reversible gates are logical basic units, having equal number of input and output lines, which can reduce power dissipation in digital systems design through their reversibility feature; because there is a one-to-one corresponding between their input and outputs vectors. The most significant aspect of the MOG gate is that it is a universal gate and has the ability of calculating any logical function on its own. We have also proposed quantum representation of the MOG gate with optimal quantum cost equal to 11. Then, it has been proved that MOG gate can be used to produce a cost efficient reversible full adder/subtractor cell in terms of reversible and quantum metrics. The proposed reversible full adder/subtractor design using MOG gate is a completely optimized circuit in terms of the number of reversible gates, the number of constant inputs, and the number of garbage outputs because it can work with the minimum possible amounts of these reversible metrics. Additionally, it is more efficient than the existing counterparts in terms of quantum cost. The full adder/subtractor cell is an important circuit in VLSI and digital signal processing applications. A lot of works have been done toward designing reversible full adder/subtractors in the literature; but there is no an optimized design with quantum implementation. To prove the applicability of the proposed design in large processing scales, we have constructed 8-bits reversible ripple carry full adder/subtractor circuit using MOG gates. Results have shown the superiority of our proposed design compared with other 8-bits similar designs.
Cite This Paper
Shekoofeh Moghimi, Mohammad R. Reshadinezhad, "A Novel 4×4 Universal Reversible Gate as a Cost Efficient Full Adder/Subtractor in Terms of Reversible and Quantum Metrics", International Journal of Modern Education and Computer Science (IJMECS), vol.7, no.11, pp.28-34, 2015. DOI:10.5815/ijmecs.2015.11.04
Reference
[1]M. R. Reshadinezhad, M. H. Moaiyeri, and K. Navi, “An energy-efficient full adder cell using CNFET technology,” IEICE transactions on electronics, vol. 95, no. 4, 2012, pp. 744-751.
[2]K. Navi, A. Doostaregan, M. H. Moaiyeri, O. Hashempour, “A hardware-friendly arithmetic method and efficientimplementations for designing digital fazzy adders,” Fuzzy Sets and Systems, vol. 185, no.1, pp. 111-124, 2011.
[3]M. R. Reshadinezhad, N. Charmchi, K. Navi,” Design and Implementation of a Three-operand Multiplier through Carbon Nanotube Technology,” International Journal of Modern Education and Computer Science (IJMECS), vol.7, no. 9, pp. 44-51.
[4]M. R. Reshadinezhad, and F. K. Samani, “A novel low complexity Combinational RNS multiplier using parallel prefix adder,” International Journal of Computer Science Issues (IJCSI), vol. 10, 2013, no. 2.
[5]M. R. Reshadinezhad, and K. Navi, “High-speed multiplier design using multi-operand multipliers,” International Journal of Computer Science and Network, 2012.
[6]J.C. Maxwell, “Theory of heat”, fourth ed., Green and Co, Longmans, 1875.
[7]L. Szilard, “On the decrease of entropy in a thermodynamic system by the intervention of intelligent beings maxwell’s demon 2 entropy”, Class. Quant. Inf. Comput. 840–856, 1929.
[8]R. Landauer, “Irreversibility and heat generation in the computing process”, IBM J. Res. Dev. 5 (3) 183–191, 1961.
[9]G. Moore, "Cramming more components onto integrated circuits", Electronics Magazine, Vol. 38, No. 8, April 19, 1965.
[10] C.H. Bennett, “Logical reversibility of computation”, IBM J. Res. Dev. 17 (6), 525–532, 1973.
[11]A. D. Vos, Y. V. Rentergem, “Power consumption in reversible logic addressed by a ramp voltage,” in Proc. of the 15 th International Workshop Patmos, LNCS, vol. 3728, , pp. 207–216, Oct. 2005.
[12]M. A. Nielsen and I. L. Chuang, “Quantum computation and quantum information”, New York: Cambridge Univ. Press, 2000.
[13]A.M. Steane, E.G. Rieffel, “Beyond bits: the future of quantum information processing”, IEEE Computer, Vol.33, No.1, pp.38-45, 2000.
[14]F. Sharmin, M.M.A. Polash, M. Shamsujjoha, L. Jamal, H.M. Hasan Babu, “Design of a compact reversible random access memory”, Fourth IEEE International Conference on Computer Science and Information Technology, vol. 10, pp. 103–107, Chengdu, China, 2011.
[15]M. Perkowski, L. Joziwak, A. Mixhchenko, A. Al-Rabadi, A. Coppola, A. Buller, X. Song, M. Khan, S. Yanushkevich, V. P. Shmerko, M.Chrzanowska-Jeske. “A general decomposition for reversible logic”, In Proceedings of the International Workshop on Methods and Representations, 2001.
[16]M. Poornima, M.S. Suma, N. Palecha, T. Malavika, “Fault tolerant reversible logic for combinational circuits: A survey”, Proceeding of International Conference on VLSI, Communication, Advanced Devices, Signal and Systems and networking, Springer, India, 2013.
[17]A. Barenco, C.H. Bennet, R.C. Leve, D.P.Divinceno, N.Margolus, P.Shor, T.Sleator, J.Smolin, h.weinfurter, ”Elementary gates for quantum computation”, Physical review A, Vol.52, Issue. 5, pp.3457-3467, March 1995.
[18]E.Fredkin, T.Toffoli, “Consevative logic”, International Journal Theoretical Physics, Vol.21, Nos.3-4, pp.219-253, 1982.
[19]M.Mohammadi, M. Eshghi, M. Haghparast, A. Bahrololoom, “Design and optimization of reversible BCD adder/subtractor circuit for quantum and nanotechnology based systems”, World Applied Sciences Journal 4(6): 787-792, 2008.
[20]M.Haghparast, K.Navi, “A novel reversible BCD adder for nanotechnology based systems”, American Journal of Applied Sciences, Vol.5, Issue 3, pp.282-288, 2008.
[21]A. Peres, “Reversible logic and quantum computers”, Physical Review A, Vol. 32, pp.3266-3276, 1985.
[22]H.G. Rangaraju, U. Venugopal, K.N. Muralidhara,K.B. Raja, “Design of efficient reversible parallel Binary adder/subtractor” CNC 2011, CCIS 142, pp. 83–87, Springer-Verlag Berlin Heidelberg, 2011.
[23]R.P. Feynman, “Quantum mechanical computers”, Optic News, Vol.11, p.11, Feb. 1985.
[24]V.Kamalakannan, Shilpakala.V, Ravi.H.N, ”Design of adder/subtractor circuit based on reversible gates”, International Journal of Advanced Research in Electrical Electronics and Instrumentation Engineering, Vol. 2, Issue 8, August, 2013.
[25]J. Kaur, H. Kaur, “Synthesis and designing of reversible adder/subtracter circuits” International Journal of Advanced Research in Electrical Electronics and Instrumentation engineering, Vol. 3, Issue 5, 2014.