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International Journal of Modern Education and Computer Science (IJMECS)

ISSN: 2075-0161 (Print), ISSN: 2075-017X (Online)

Published By: MECS Press

IJMECS Vol.8, No.8, Aug. 2016

Fault Tolerant ALU using Parity Preserving Reversible Logic Gates

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Author(s)

Shaveta Thakral, Dipali Bansal

Index Terms

ALU;Fault tolerant;Power Dissipation;GSI;Quantum Cost;Reliable computing

Abstract

Demand of reliable computing has been a major concern since the dawn of the electronic digital computer age. Reliable computing has various applications not only in the field of military, aerospace and communication but even contemporary commercial applications to fulfill today's automated life style. The tremendous growth in fabrication from small scale integration (SSI) to giant scale integration (GSI) is facing power dissipation as one of the main barriers. To overcome this barrier, researchers need to enter into the reversible logic domain. Making a reversible circuit robust or fault tolerant is much more difficult than a conventional logic circuit. Fault tolerance can be achieved in a system by using parity bits. The main aim of this paper is to come up with a new fault tolerant ALU design based on parity preserving reversible logic gates with improved quantum cost and power overhead as compare to existing fault tolerance based ALU designs. The most stringent requirement for fault tolerant ALU is in real time control system where faulty computation jeopardizes human life or other catastrophic effects.Implentation of proposed design is done using Xilinx ISE design suit 14.2 tool and its performance over existing ALU designs is qualitatively analyzed.

Cite This Paper

Shaveta Thakral, Dipali Bansal,"Fault Tolerant ALU using Parity Preserving Reversible Logic Gates", International Journal of Modern Education and Computer Science(IJMECS), Vol.8, No.8, pp.51-58, 2016.DOI: 10.5815/ijmecs.2016.08.07

Reference

[1]R.Landauer, "Irreversibility and heat generation in the computing process", IBM Journal of Research and Development, vol.5, no.3, pp.183-191, 1961

[2]C.Bennett," Logical reversibility of computation",IBM Journal of Research and Development, vol.17, no.6, pp.525-532,1973

[3]B.Sen, S. Ganeriwal and B.Sikdar,"Reversible logic-based fault-tolerant nanocircuits in QCA", ISRN Electronics, pp.1-9, 2013

[4]R.Saligram, S.H. Shridhar, A.S. Kulkarni, , H.R, B. and M.K, "Design of parity preserving logic based fault tolerant reversible arithmetic logic unit", International Journal of VLSI Design & Communication Systems, vol. 4, no.3, pp.53-68,2013

[5]M.Islam and Z.Begum,"Reversible logic synthesis of fault tolerant carry skip BCD adder", Journal of Bangladesh Academy of Sciences,vol. 32, no.2., 2009

[6]M.Morrison, M. Lewandowski,R. Meana,and N.Ranganathan, "Design of a novel reversible ALU using an enhanced carry look- ahead adder",. 11th IEEE International Conference on Nanotechnology. Portland, Oregon, USA, IEEE, pp.1436-1440,2011

[7]Y.Syamala and A.TIlak," Reversible arithmetic logic unit",Electronics Computer Technology (ICECT), 3rd International Conference, Kanyakumari.IEEE, pp.207-211,2011

[8]Z.Guan, W. Li, W.Ding, Y. Hang and L.Ni, L,"An arithmetic logic unit design based on reversible logic gates",Communications, Computers and Signal Processing (PacRim), 2011 IEEE Pacific Rim Conference, Victoria, BC: IEEE, pp.925-931,2011

[9]R.Singh, S. Upadhyay, S. S, J.KB, and H.SA, "Efficient design of arithmetic logic unit using reversible logic gates, International Journal of Advanced Research in Computer Engineering & Technology (IJARCET), vol.3, no. 4, pp.1474-1477,2014

[10]V.Veravalli, "Fault tolerance for arithmetic and logic unit",IEEE Southeastcon ,Atlanta, GA,IEEE, pp.329-334,2009

[11]T.Rakshith and R.Saligram," Parity preserving logic based fault tolerant reversible ALU", Information & Communication Technologies (ICT), 2013 IEEE Conference. JeJu Island, IEEE, pp.485-490, 2013

[12]N.Sharma, R. Sachdeva, U.Saraswat,R.Yadav and G.Kaur, "Power efficient arithmetic logic unit design using reversible logic",International Journal of Computer Applications, vol.128, no.6, pp.36-41,2015

[13]A.Majumdar, S. Nayyar and J.Sengar,"Fault tolerant ALU system",Computing Sciences (ICCS), 2012 International Conference, Phagwara, IEEE, pp.255-260,2012

[14]V.Khorasani,B. Vahdat and M.Mortazavi, "Analyzing area penalty of 32-Bit fault tolerant ALU using BCH code, Digital System Design (DSD), 2011 14th Euromicro Conference, Oulu, IEEE, pp.409-413, 2011

[15]K.Arunachalam, M. Perumalsamy, C. Sundaram, and J.Kumar, " Design and implementation of a reversible logic based 8-Bit arithmetic and logic Unit", International Journal of Computers and Applications.,Vol.36, no.2, pp. 49-55,2014