INFORMATION CHANGE THE WORLD

International Journal of Computer Network and Information Security(IJCNIS)

ISSN: 2074-9090 (Print), ISSN: 2074-9104 (Online)

Published By: MECS Press

IJCNIS Vol.11, No.12, Dec. 2019

Design and Implementation of Runtime Reconfigurable Encryption Algorithms using Custom ICAP Processor

Full Text (PDF, 611KB), PP.10-16


Views:0   Downloads:0

Author(s)

Jamuna S, Dinesha P, K PShashikala, Kishore Kumar K

Index Terms

Encryption;FPGA;ICAP Processor;Partial Reconfiguration

Abstract

Field programmable gate arrays (FPGAs) are the reconfigurable logic devices which are widely used in many applications like space missions, automotive electronics, complex computing systems and system prototyping. Run time reconfigurability feature supported in high end FPGAs allows the designer to optimize design with respect to resource utilization and power consumption. Using partial reconfiguration a specific part of the FPGA can be reconfigured at run time without altering the original design. In data communication, safety and confidentiality of data is achieved through a suitable encryption algorithm. Encryption is most important aspect when it comes to security. Design flexibility can be increased by providing an option to the user to select a particular algorithm as per the requirement. Instead of using a single algorithm to encrypt data, multiple algorithms can be used with an option to switch between the algorithms. Thus optimizing the resource utilization and also can avoid security breach. Through this work, an attempt is made to include reconfiguration of the design at run-time. This design implements different encryption algorithms at different instance of time. In this paper two encryption algorithms i.e. Advance Encryption Standard (AES) and TwoFish both of 128-bit are chosen to reconfigure at runtime using a custom ICAP (Internal Configuration Access Port) controller IP provided by Xilinx and is implemented on Zedboard. Main advantage of this implementation is that the user have an option to switch between two algorithms, thus helping in overall resource optimization.

Cite This Paper

Jamuna S, Dinesha P, K PShashikala, Kishore Kumar K, "Design and Implementation of Runtime Reconfigurable Encryption Algorithms using Custom ICAP Processor", International Journal of Computer Network and Information Security(IJCNIS), Vol.11, No.12, pp.10-16, 2019. DOI: 10.5815/ijcnis.2019.12.02

Reference

[1]Xilinx “Partial Reconfiguration User Guide” UG 702.

[2]“Practical cryptography”, Text book Ferguson N. Schneier B. Wiley, 2003 ISBN-0471223573, 9780471223573.

[3]Xilinx “7 Series FPGAs Configuration User Guide” UG470.

[4]Divya, Dinesha P, Jamuna S, “ Implementation of Advanced Encryption standard in Vivado Design suite” JEITR, volume 5, August 2018

[5]Aparna. K, Jyothy Solomon, Harini . M, Indhumathi “A Study of Twofish Algorithm” 2016 IJEDR | Volume 4, Issue 2 | ISSN: 2321-9939

[6]Sanjay Kumar, Shashi Bhushan Thakur, Yogesh, Sanjeeth and Dr. Jamuna S, " Design and Implementation of Two Fish Encryption algorithm on ZED board", IJSRR, Volume 8, Issue 5, May 2019

[7]Yuwen Zhu, Hongqi Zhang, YibaoBao “Study of the AES Realization Method on the Reconfigurable Hardware,” 2013 International Conference on Computer Sciences and Applications. DOI: 10.1109/CSA.2013.23

[8]Ye Yuan, Yijun Yang, Liji Wu, Xiangmin Zhang , “A High Performance Encryption System Based on AES Algorithm with Novel Hardware Implementation,” IEEE conference. DOI: 10.1109/EDSSC.2018.8487056

[9]S. Burman, P. Rangababu and K. Datta, "Development of dynamic reconfiguration implementation of AES on FPGA platform," 2017 Devices for Integrated Circuit (DevIC), Kalyani, 2017, pp. 247-251. DOI: 10.1109/DEVIC. 2017. 8073945.

[10]SnehalWankhade and Rashmi Mahajan. “Dynamic partial reconfiguration implementation of AES algorithm,” International Journal of Computer Applications, 97(3), 2014. DOI: 10.5120/16986-7084

[11]R. Yegireddi and R. K. Kumar, "A survey on conventional encryption algorithms of Cryptography," 2016 International Conference on ICT in Business Industry & Government (ICTBIG), Indore, 2016, pp.1-4. DOI: 10.1109/ ICTBIG. 2016.7892684.

[12]S. A. M. Rizvi, S. Z. Hussain and N. Wadhwa, "Performance Analysis of AES and TwoFish Encryption Schemes," 2011 International Conference on Communication Systems and Network Technologies,Katra, Jammu, 2011, pp. 76-79. DOI: 10.1109/CSNT.2011.160.

[13]M. Panda, "Performance analysis of encryption algorithms for security," 2016 International Conference on Signal Processing, Communication, Power and Embedded System (SCOPES), Paralakhemundi, 2016, pp. 278-284.DOI: 10.1109/SCOPES.2016.7955835.

[14]Pil-Joong Kang, Seon-Keun Lee and Hwan-Yong Kim, "Study on the design of MDS-M2 Twofish cryptographic algorithm adapted to wireless communication," 2006 8th International Conference Advanced Communication Technology, Phoenix Park, 2006, pp. 4 pp.-695.DOI: 10.1109/ICACT.2006.206060.

[15]Zine El AbidineAlaouiIsmaili and Ahmed Moussa. Self-partial and dynamic reconfiguration implementation for aes using fpga. ArXiv preprint arXiv:0909.2369, 2009.

[16]PUB FIPS. 197, advanced encryption standard (aes), national institute of standards and technology, us department of commerce (November 2001). Link in: http://csrc. nist. gov/publications/fips/fips197/fips-197, 2009.

[17]PawelChodowiec, Po Khuon, and Kris Gaj. Fast implementations of secret-key block ciphers using mixed inner-and outer-round pipelining. In Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, pages 94–102. ACM, 2001.

[18]Jos´e M Granado-Criado, Miguel A Vega-Rodr´ıguez, Juan M S´anchez- P´erez, and Juan A G´omez-Pulido. A new methodology to implement the aes algorithm using partial and dynamic reconfiguration. INTEGRATION, the VLSI journal, 43(1):72–80, 2010.