Designing a reliable system on reconfigurable devices has become a significant factor for implementing mission critical applications like communication protocols, automotive, nuclear reactor control, and remote applications. With the improvement in fabrication technology, logic density of the field programmable gate arrays has increased rapidly. Because of decrease in feature size, integrated circuits are becoming vulnerable to errors and also the ageing component results in run time faults. FPGAs when used in harsh conditions like high radiation and temperatures, there is a possibility of getting affected by transient faults or the soft errors. In digital communication, safety and confidentiality of data is achieved through a suitable encryption algorithm. Encryption is most important aspect when it comes to security. Reliable design techniques are very much necessary for maintaining the system’s normal function. Many of the available techniques are based on redundancy logic causing area overhead for the design. Through this paper, an implementation is illustrated for managing soft errors or the single event upsets. Proposed methodology identifies and avoids the errors occurring at the logic resources where the encryption algorithms are mapped on the device. Thus encryption algorithms work normally without getting affected by the errors. During the simulation process, errors are injected at the configuration memory frames and monitored using a Single event-upset manager (SEM) controller. The proposed design is implemented on Zedboard using Xilinx Vivado 2017.4.

Field programmable gate arrays (FPGAs) are the reconfigurable logic devices which are widely used in many applications like space missions, automotive electronics, complex computing systems and system prototyping. Run time reconfigurability feature supported in high end FPGAs allows the designer to optimize design with respect to resource utilization and power consumption. Using partial reconfiguration a specific part of the FPGA can be reconfigured at run time without altering the original design. In data communication, safety and confidentiality of data is achieved through a suitable encryption algorithm. Encryption is most important aspect when it comes to security. Design flexibility can be increased by providing an option to the user to select a particular algorithm as per the requirement. Instead of using a single algorithm to encrypt data, multiple algorithms can be used with an option to switch between the algorithms. Thus optimizing the resource utilization and also can avoid security breach. Through this work, an attempt is made to include reconfiguration of the design at run-time. This design implements different encryption algorithms at different instance of time. In this paper two encryption algorithms i.e. Advance Encryption Standard (AES) and TwoFish both of 128-bit are chosen to reconfigure at runtime using a custom ICAP (Internal Configuration Access Port) controller IP provided by Xilinx and is implemented on Zedboard. Main advantage of this implementation is that the user have an option to switch between two algorithms, thus helping in overall resource optimization.