IJCNIS Vol. 12, No. 4, 8 Aug. 2020
Cover page and Table of Contents: PDF (size: 569KB)
Full Text (PDF, 569KB), PP.41-50
Views: 0 Downloads: 0
Encryption, Fault Tolerance, SEM Controller, Partial Reconfiguration, PGA
Designing a reliable system on reconfigurable devices has become a significant factor for implementing mission critical applications like communication protocols, automotive, nuclear reactor control, and remote applications. With the improvement in fabrication technology, logic density of the field programmable gate arrays has increased rapidly. Because of decrease in feature size, integrated circuits are becoming vulnerable to errors and also the ageing component results in run time faults. FPGAs when used in harsh conditions like high radiation and temperatures, there is a possibility of getting affected by transient faults or the soft errors. In digital communication, safety and confidentiality of data is achieved through a suitable encryption algorithm. Encryption is most important aspect when it comes to security. Reliable design techniques are very much necessary for maintaining the system’s normal function. Many of the available techniques are based on redundancy logic causing area overhead for the design. Through this paper, an implementation is illustrated for managing soft errors or the single event upsets. Proposed methodology identifies and avoids the errors occurring at the logic resources where the encryption algorithms are mapped on the device. Thus encryption algorithms work normally without getting affected by the errors. During the simulation process, errors are injected at the configuration memory frames and monitored using a Single event-upset manager (SEM) controller. The proposed design is implemented on Zedboard using Xilinx Vivado 2017.4.
Jamuna S, Dinesha P, Kp Shashikala, Kishore Kumar K, "Design and Implementation of Reliable Encryption Algorithms through Soft Error Mitigation", International Journal of Computer Network and Information Security(IJCNIS), Vol.12, No.4, pp.41-50, 2020. DOI:10.5815/ijcnis.2020.04.04
[1]B. Harikrishna and S. Ravi, "A survey on fault tolerance in FPGAs," 2013 7th International Conference on Intelligent Systems and Control (ISCO), Coimbatore, 2013, pp. 265-270. doi: 10.1109/ISCO.2013.6481160.
[2]“Practical cryptography”, Text book Ferguson N. Schneier B. Wiley, 2003 ISBN-0471223573, 9780471223573.
[3]Ye Yuan, Yijun Yang, Liji Wu, Xiangmin Zhang , “A High Performance Encryption System Based on AES Algorithm with Novel Hardware Implementation,” IEEE conference, 2018. DOI: 10.1109/EDSSC.2018.8487056
[4]S. Burman, P. Rangababu and K. Datta, "Development of dynamic reconfiguration implementation of AES on FPGA platform," 2017 Devices for Integrated Circuit (DevIC), Kalyani, 2017, pp. 247-251. DOI: 10.1109/DEVIC. 2017. 8073945.
[5]Snehal Wankhade and Rashmi Mahajan. “Dynamic partial reconfiguration implementation of AES algorithm,” International Journal of Computer Applications, 97(3), 2014. DOI: 10.5120/16986-7084
[6]R. Yegireddi and R. K. Kumar, "A survey on conventional encryption algorithms of Cryptography," 2016 International Conference on ICT in Business Industry & Government (ICTBIG), Indore, 2016, pp.1-4. DOI: 10.1109/ ICTBIG. 2016.7892684.
[7]S. A. M. Rizvi, S. Z. Hussain and N. Wadhwa, "Performance Analysis of AES and TwoFish Encryption Schemes," 2011 International Conference on Communication Systems and Network Technologies, Katra, Jammu, 2011, pp. 76-79. DOI: 10.1109/CSNT.2011.160.
[8]Xilinx “Partial Reconfiguration User Guide” UG 702.
[9]Xilinx “Soft Error Mitigation Controller” Product Guide, PG036.
[10]A. Adetomi, G. Enemali and T. Arslan, "A fault-tolerant ICAP controller with a selective-area soft error mitigation engine," 2017 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Pasadena, CA, 2017, pp. 192-199. doi: 10.1109/AHS.2017.8046378.
[11]S. Mandal, R. Paul, S. Sau, A. Chakrabarti and S. Chattopadhyay, "A Novel Method for Soft Error Mitigation in FPGA Using Modified Matrix Code," in IEEE Embedded Systems Letters, vol. 8, no. 4, pp. 65-68, Dec. 2016. doi: 10.1109/LES.2016.2603918.
[12]T. S. Nidhin, A. Bhattacharyya, R. P. Behera, T. Jayanthi and K. Velusamy, "Dependable system design with soft error mitigation techniques in SRAM based FPGAs," 2017 Innovations in Power and Advanced Computing Technologies (i-PACT), Vellore, 2017, pp. 1-6. doi: 10.1109/IPACT.2017.8244907.
[13]M. E. Keshk and K. Asami, “fault injection in dynamic partial reconfiguration design based on essential bits”, jast, vol. 11, no. 2, pp. 25-34, jul. 2018.
[14]A. Sari and M. Psarakis, "A fault injection platform for the analysis of soft error effects in FPGA soft processors," 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Kosice, 2016, pp. 1-6.doi: 10.1109/DDECS.2016.7482459.
[15]N. Jing, J. Lee, W. He, Z. Mao and L. He, "Mitigating FPGA interconnect soft errors by in-place LUT inversion," 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, 2011, pp. 582-586. doi: 10.1109/ICCAD.2011.6105389.
[16]Xilinx “7 Series FPGAs Configuration User Guide” UG470.
[17]Yuwen Zhu, Hongqi Zhang, Yibao Bao “Study of the AES Realization Method on the Reconfigurable Hardware,” 2013 International Conference on Computer Sciences and Applications. DOI: 10.1109/CSA.2013.23.